*Proc. of ISPASS'06 - IEEE International Symposium on Performance Analysis of Systems and Software,*pp. 112-119, Mar. 2006.

[GKK05] A. Goel, I. Koren and C. M. Krishna, "Energy Aware Kernel for Hard Real-Time Systems," (pdf file)

*Proc. of the IEEE Conf. on Compilers, Architectures for Embedded Systems - CASES 2005*, pp. 185-190, Sept. 2005.

[WoKo05] Z. Wo and I. Koren, "Synthesis of Saturating Counters Using Traditional and Non-traditional Basic Counters,"(pdf file)

*Proc. of the 17th IEEE Symp. on Computer Arithmetic*, pp. 114-121, June 2005.

[WoKC05] Z. Wo, I. Koren and M. Ciesielski, "An ILP Formulation for Yield-driven Architectural synthesis," (pdf file)

*Proc. of the 2005 IEEE Intern. Symp. on Defect and Fault Tolerance in VLSI Systems,*pp. 12-20, Oct. 2005.

[WoKo05a] Z. Wo and I. Koren, "Technology Mapping for Reliability Enhancement in Logic Synthesis," (pdf file)

*Proc. of the International Symp. on Quality of Electronic Design (ISQED'05),*pp. 137-142, March 2005.

[WoKo05b] Z. Wo and I. Koren, "Effective Analytical Delay Model for Transistor Sizing," (pdf file)

*Proc. of the ASP-DAC 2005 Conf.,*pp. 387-392, Jan. 2005.

[ChKo04] G. Chapman, Y. Audet, S. Djaja, D. Cheung, I. Koren and Z. Koren, "Self-Correcting Active Pixel Sensor using Hardware and Software Correction,"(pdf file)

*IEEE Design & Test of Computers,*pp. 544-551, Nov. 2004.

[UKKM04] O. S. Unsal, I. Koren, C.M. Krishna, C.A. Moritz, "Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction", (pdf file)

*Proc. of INTERACT-8 organized in conjunction with HPCA-10,*February 2004.

[MaKB04] A. Maheshwari, I. Koren and W. Burleson, "Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits," (pdf file)

*Proc. of the 2004 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 377-385, October 2004.

[GCKKM04] Y. Guo, S. Chheda, I. Koren, C. M. Krishna, and C. A. Moritz, "Energy-Aware Data Prefetching for General-Purpose Programs," (pdf file)

*Proc. of PACS'04 Workshop on Power-Aware Computer Systems, Micro-37,*pp. 51-59, Dec. 2004.

[YKK04] H. Yang, I. Koren, C.M. Krishna, "Incorporating Application-Level Fault Tolerance and Detection into Radar Angular Super-Resolution," (pdf file)

*Proc. of the 10th IEEE Pacific Rim International Symp. on Dependable Computing (PRDC 2004),*pp. S:1-2, March 2004.

[SiKo03] M. Singh and I. Koren, "Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters," (pdf file)

*IEEE Trans. on VLSI Systems*, pp. 839-852, Nov. 2003.

[SiKo03a] M. Singh and I. Koren, "Fault Sensitivity and Tolerance of the Successive Approximation and Delta-Sigma Analog-to-Digital Converters," (pdf file)

*International Journal of Analog Integrated Circuits and Signal Processing,*Vol. 35, Special Issue on Quality Electronic Design, pp. 189-197, May 2003.

[MaKB03] A. Maheshwari, I. Koren and W. Burleson, "Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits," (pdf file)

*Proc. of the 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 597-604, November 2003.

[LaKK03] V. Lakamraju, I. Koren and C.M. Krishna, "Low Overhead Fault Tolerant Networking in Myrinet," (pdf file)

*Proc. of the Dependable Computing and Communication Symp. (DSN),*pp. 193-202, June 2003.

[UnKo03] O.S. Unsal and I. Koren, "System-Level Power-Aware Design Techniques in Real-Time Systems," (Invited paper) (pdf file)

*Proceedings of the IEEE*, pp. 1055-1069, July 2003.

[UAKKM03] O.S. Unsal, R. Ashok, I. Koren, C.M. Krishna and C. A. Moritz, "Cool-Cache: A Compiler-Enabled Energy Efficient Data Caching Framework for Embedded/Multimedia Processors," (pdf file),

*ACM Transactions on Embedded Computing Systems,*Special Issue on Power-Aware Systems, pp. 373-392, August 2003.

[BBKMP03a] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm," (pdf file),

*Proc. of ASAP'03 - the Internl. Conference on Application-Specific Systems, Architectures and Processors,*pp. 423-432, June 2003.

[BBKMP03b] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard," (pdf file),

*Proc. of the 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 105-113, Nov. 2003.

[KKO03] I. Koren, Y. Koren and B. Oomman, "Saturating Counters: Application and Design Alternatives," (pdf file),

*Proc. of the 16th IEEE Symp. on Computer Arithmetic*, pp. 228-235, June 2003.

[BBKMP03] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard," (pdf file),

*IEEE Trans. on Computers,*pp. 492-505, April 2003.

[LAKK02] V. Lakamraju, I. Koren and C.M. Krishna, "Filtering Random Networks to Synthesize Interconnection Networks with Multiple Objectives," (pdf file)

*IEEE Transactions on Parallel and Distributed Systems,*pp. 1139-1149, October 2002.

[UKKM02a] O.S. Unsal, I. Koren, C.M. Krishna and C. A. Moritz, "Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling," (pdf file)

*Computer Architecture Letters,*Vol. 1, pp. 6-9, July 2002.

[UKKM02b] O.S. Unsal, I. Koren, C.M. Krishna and C. A. Moritz, "The Minimax Cache: An Energy-Efficient Framework for Media Processors," (pdf file)

*Proc. of the 2002 International Symp. on High Performance Computer Architecture (HPCA 2002),*pp. 131-140, Feb. 2002.

[SiK002] M. Singh and I. Koren, "Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)," (pdf file)

*Proc. of the International Symposium on Quality of Electronic Design (ISQED'02),*pp. 286-291, March 2002.

[KaIK02] R. Karri, B. Iyer and I. Koren, "Phantom Redundancy: A Register Transfer Level Technique for Gracefully Degradable Data Path Synthesis," (pdf file)

*IEEE Trans. on Computer-Aided Design,*pp. 877-888, August 2002.

[KRKK02] Z. Koren, J. Rajagopal, C. M. Krishna, I. Koren, W. Wang and J. Loman, "Using Rational Approximations For Evaluating The Reliability of Highly Reliable Systems," (pdf file)

*Proc. of the PMEO-PDS'02 workshop, IPDPS,*pp. 258-263, April 2002.

[KoKo02] Z. Koren and I. Koren, "Analysis of a Flexible Redundancy Technique for Multi-Bank Memory ICs," (pdf file)

*Proc. of the European Test Workshop (ETW 2002),*May 2002.

[URKK01] O. Unsal, A. Raksit, I. Koren, C. M. Krishna, and C.A. Moritz, "Cool Cache for Hot Multimedia," (pdf file)

*Proc. of MICRO'34, The international Sympo. on Microarchitecture*, pp. 274-283, Dec. 2001.

[PhGK01] D.S. Phatak, T. Goff and I. Koren, "Constant-time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations," (pdf file)

*IEEE Trans. on Computers*, pp. 1267-1278, Nov. 2001.

[DuKK01] G. Durairaj, I. Koren and C.M. Krishna, "Importance Sampling to Evaluate Real-Time System Reliability: A Case Study," (pdf file)

*Simulation*, vol. 76, no. 3, pp. 172-183, March 2001.

[SiKo01] M. Singh and I. Koren, "Reliability Enhancement of Analog-to-Digital Converters (ADCs)," (pdf file)

*Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 347-353, October 2001.

[KoCK01] I. Koren, G. Chapman and Z. Koren, "Advanced Fault-Tolerance Techniques for a Color Digital Camera-On-A-Chip, " (pdf file)

*Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 3-10, October 2001.

[SiRK01] M. Singh, R. Rachala and I. Koren, "Transient Fault Sensitivity Analysis of Analog-to-Digital Converters," (pdf file)

*Proc. of WVLSI 2001,*April 2001.

[PrKo01] R. K. Prasad and I. Koren, "Constructive Floorplanning with a Yield Objective," (pdf file)

*Proc. of the International Symposium on Quality of Electronic Design,*pp. 261-266, March 2001.

[PGKo01] D.S. Phatak, T. Goff and I. Koren, "Constant-time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations," (pdf file)

*IEEE Trans. on Computers,*pp. 1267-1278, Nov. 2001.

[AKK01] E. Asai, I. Koren and C. M. Krishna, "A Web/DVD-Based Multimedia Architecture Simulator," (pdf file)

*Proc. of Frontiers in Education, FIE 2001,*pp. T3F.14-19, October 2001.

[KoKo00] I. Koren and Z. Koren, "Incorporating Yield Enhancement into the Floorplanning Process," (pdf file)

*IEEE Trans. on Computers, Special Issue on Defect Tolerance in Digital Systems*, Vol. 49, pp. 532-541, June 2000.

[HLKK00] J. Haines, V.R. Lakamraju, I. Koren and C.M. Krishna, "Application-Level Fault Tolerance as a Complement to System-Level Fault Tolerance," (pdf file)

*The Journal of Supercomputing,*Special Issue on "Embedded Fault-Tolerant Computing Systems," Vol. 16, pp. 53-68, Kluwer Academic Publishers, MA, 2000.

[ACDH00] M. Allalouf, J. Chang, G. Durairaj, J. Haines, V.R. Lakamraju, K. Toutireddy, O.S. Unsal, K. Yu, I. Koren and C.M. Krishna, "The RAPIDS Simulator: A Testbed for Evaluating Scheduling, Allocation, and Fault-Recovery in Distributed Real-Time Systems," (pdf file)

*Dependable Network Computing,*D. Avresky (Editor), pp. 413-431, Kluwer Academic Publishers, MA, 2000.

[PrKo00] R. K. Prasad and I. Koren, "The Effect of Placement on Yield for Standard Cell Designs," (pdf file)

*Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 3-11, October 2000.

[KCK00] I. Koren, G. Chapman and Z. Koren, "A Self-Correcting Active Pixel Camera," (pdf file)

*Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 56-64, October 2000.

[Ko00] I. Koren, "Should Yield be a Design Objective?" (invited paper), (pdf file)

*Proc. of the International Symposium on Quality of Electronic Design,*pp. 115-120, March 2000.

[YTKK99] K. Yu, K. Toutireddy, I. Koren and C.M. Krishna, "Introduction to a Fault-Tolerant Distributed Real-Time System Simulator," (pdf file)

*Intern. Journal of Modeling and Simulation,*Vol. 19, No. 1, pp. 7-10, 1999.

[AlKo99] D. H. Albonesi and I. Koren, "STATS: A Framework for Microprocessor and System-Level Design Space Exploration," (pdf file)

*Journal of System Architecture*, Vol. 45, pp. 1097-1110, 1999.

[PhKo99] D.S. Phatak and I. Koren, "Intermediate Variable Encodings that Enable Multiplexor-based Implementations of Two Operand Addition," (pdf file)

*Proc. of the 14th IEEE Symp. on Computer Arithmetic*, pp. pp. 22-29, April 1999.

[PGKo99] D.S. Phatak, T. Goff and I. Koren, "Redundancy Management in Arithmetic Processing via Redundant Binary Representations," invited paper, (pdf file)

*Proc. of the 33rd Asilomar Conference on Signals, Systems and Computers,*pp. 1475-1479, October 1999.

[VeKo99] A. Venkataraman and I. Koren, "Determination of yield bounds prior to routing," (pdf file)

*Proc. of the 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 4-13, November 1999.

[KoKo99] I. Koren and Z. Koren, "Floorplanning of Memory ICs: Routing Complexity vs. Yield," (pdf file)

*Proc. of the International Symp. on Microelectronic Manufacturing Technologies - Yield, Reliability and Failure Analysis (MMT04)*, May 1999.

[KoKo98] I. Koren and Z. Koren, "Defect Tolerant VLSI Circuits: Techniques and Yield Analysis," (pdf file)

*Proceedings of the IEEE*, Vol. 86, pp. 1817-1836, Sept. 1998.

Errata - equations (34)-(35).

[HLKK98] J. Haines, V.R. Lakamraju, I. Koren and C.M. Krishna, "Development of Application-Level Fault Tolerance in a Real-Time Benchmark," (pdf file)

*Proc. of EFTS'98, IEEE Workshop On Embedded Fault-Tolerant Systems,*May 1998.

[KoKo98b] I. Koren and Z. Koren, "Yield and Routing Objectives in Floorplanning," (pdf file)

*Proc. of the 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 28-36, November 1998.

[KKKr98] Z. Koren, I. Koren and C.M. Krishna, "Surge Handling as a Measure of Real-Time System Dependability," (pdf file)

*Proc. of the IPPS/SPDP'98 workshop, in Parallel and Distributed Processing,*J. Rolim (Ed.), Lecture Notes in Computer Science 1388, Springer 1998, pp. 1106-1116.

[AlKo97] D. H. Albonesi and I. Koren, "Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems," (pdf file)

*Proc. of the 1997 Conference on Parallel Architectures and Compilation Techniques*(PACT'97), pp. 126-135, Nov. 1997.

[KoKo97] Z. Koren and I. Koren, "On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits" , (pdf file)

*IEEE Trans. on VLSI Systems,*Vol. 5, pp. 3-14, March 1997.

[KoKo97a] I. Koren and Z. Koren, "Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs," (pdf file)

*Proc. of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 166-174, October 1997.

[VCKo97] A. Venkataraman, H. Chen and I. Koren, "Yield Enhanced Routing for High-Performance VLSI Designs," (pdf file)

*Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97,*pp. 50-60, September 1997.

[ChKo97] Z. Chen and I. Koren, "Crosstalk Minimization in Three-Layer HVH Channel Routing," (pdf file)

*Proc. of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems*, pp. 38-42, October 1997.

[ChKo97a] Z. Chen and I. Koren, "Three Layer Routing for Reliability Enhancement," (pdf file)

*International Journal on Microelectronics Systems Integration,*Vol 5, No 4, pp. 209-219, Dec. 1997.

[ChKo97b] Z. Chen and I. Koren, "Technology Mapping for Hot-Carrier Reliability Enhancement," (pdf file)

*Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97,*pp. 42-50, Austin, Texas, October 1997.

[ChiKo96] V.K.R. Chiluvuri and I. Koren, "Wire Length and Via Reduction for Yield Enhancement," (pdf file)

*Proc. of the 1996 SPIE Microelectronics Manufacturing Conference,*pp. 103-111, Austin, Texas, Oct. 1996.

[ChKo96] Z. Chen and I. Koren, "Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing," (pdf file)

*Proc. of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems*, pp. 76-84, November 1996.

[Ko1996] I. Koren, "Catastrophic Yield, Parametric Yield and Reliability: Can We Still View Them as Disjoint Issues?," invited position paper, (pdf file)

*Proc. of the 5th ACM/SIGDA Physical Design Workshop,*pp. 207-209, April 1996.

[VeKo96] A. Venkataraman and I. Koren, "Trade-offs between Yield and Reliability Enhancement," (pdf file)

*Proc. of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems*, pp. 67-75, November 1996.

[AlKo96] D. H. Albonesi and I. Koren, "A Mean Value Analysis Multiprocessor Model Incorporating Superscaler Processors and Latency Tolerating Techniques," (pdf file)

*International Journal of Parallel Programming,*Vol. 24, Number 3, pp. 235-263, 1996.

[KoKo96] I. Koren and Z. Koren, "Yield Analysis of a Novel Scheme for Defect-Tolerant Memories," (pdf file)

*Proc. of the 1996 IEEE International Conference on Innovative Systems in Silicon,*pp. 269-278, Austin, Texas, October 1996.

[AlKo95] D. H. Albonesi and I. Koren, "Architecture and Technology Tradeoffs in the Design of Next-Generation Multiprocessor Servers," (pdf file)

*Proc. of the 7th IEEE Sympos. on Parallel and Distributed Processing,*(SPDP'95), pp. 174-181, Oct. 1995.

[AlKo95a] D. H. Albonesi and I. Koren, "An Analytical Model of High Performance Superscaler-Based Multiprocessors," (pdf file)

*Proc. of the 1995 Internl. Conf. on Parallel Architectures and Compilation Techniques (PACT'95),*pp. 194-203, June 1995.

[LaKo95a] P. Lalwaney and I. Koren, "Fault-Tolerance in Optically Interconnected Multiprocessor Networks," (pdf file)

*Fault-Tolerant Parallel and Distributed Systems,*D. Pradhan and D. Avresky (Editors), pp. 91-98, IEEE Comp. Society Press, Los Alamitos, CA, 1995.

[LaKo95b] P. Lalwaney and I. Koren, "Fault-Tolerance Schemes for WDM-Based Multiprocessor Networks," (pdf file)

*Proc. of the 2nd Intern. Conference on Massively Parallel Processing using Optical Interconnections*, pp. 90-97, Oct. 1995.

[PhKo95] D.S. Phatak and I. Koren, "Complete and Partial Fault Tolerance of Feedforward Neural Nets," (pdf file)

*IEEE Trans. on Neural Nets,*Vol. 6, pp. 446-456, March 1995.

[WaKo95] I. A. Wagner and I. Koren, "An Interactive VLSI CAD Tool for Yield Estimation," (pdf file)

*IEEE Trans. on Semiconductor Manufacturing,*Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 130-138, May 1995.

[WaKo95b] I. A. Wagner and I. Koren, "The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines," (pdf file)

*Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 46-54, November 1995.

[YuKo95] K. Yu and I. Koren, "Reliability Enhancement of Real-Time Multiprocessor Systems through Dynamic Reconfiguration," (pdf file)

*Fault-Tolerant Parallel and Distributed Systems,*D. Pradhan and D. Avresky (Editors), pp. 161-168, IEEE Computer Society Press, Los Alamitos, CA, 1995.

[IyKK95] B. Iyer, R. Karri and I. Koren, "Phantom Redundancy: A High-Level Synthesis Technique for Manufacturability," (pdf file)

*Proc. of ICCAD-95, The Internl. Conference on CAD,*pp. 658-661, Nov. 1995.

[ChiKo95] V.K.R. Chiluvuri and I. Koren, "Layout Synthesis Techniques for Yield Enhancement," (pdf file)

*IEEE Trans. on Semiconductor Manufacturing,*Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 178-187, May 1995 (Won the 1995 Best Paper Award of the

*IEEE Trans. on Semiconductor Manufacturing.*).

[ChiKo95a] V.K.R. Chiluvuri and I. Koren, "Yield Enhancement vs. Performance Improvement in VLSI Circuits," (pdf file)

*Proc. of ISSM-95, The Intern. Symp. on Semiconductor Manufacturing,*pp. 28-31, Austin, Sept. 1995.

[PhKo95] D.S. Phatak and I. Koren, "Complete and Partial Fault Tolerance of Feedforward Neural Nets," (pdf file)

*IEEE Trans. on Neural Nets*, Vol. 6, pp. 446-456, March 1995.

[ChKo95] Z. Chen and I. Koren, "Techniques for Yield Enhancement of VLSI Adders," (pdf file)

*Proc. of ASAP 95 - the Internl. Conference on Application-Specific Array Processors,*pp. 222-229, July 1995.

[ChKo95a] Z. Chen and I. Koren, "Layer Assignment for Yield Enhancement," (pdf file)

*Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 173-180, November 1995.

[KoKo1995] Z. Koren and I. Koren, "The Impact of Floorplanning on the Yield of Fault-Tolerant ICs," (pdf file)

*Proc. of Internl. Conf. on Wafer Scale Integration,*pp. 329-338, Jan. 1995.

[LaKo94] P. Lalwaney and I. Koren, "Reconfigurable Optical Interconnects for Computer Vision Applications," (pdf file)

*Proc. of the 1st Intern. Workshop on Massively Parallel Processing using Optical Interconnections,*pp. 224-236, April 1994.

[ChiKB94] V.K.R. Chiluvuri, I. Koren and J. L. Burns, "The Effect of Wire Length Minimization on Yield," (pdf file)

*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 97-105, October 1994.

[ChKo94] Z. Chen and I. Koren, "A Yield Study of VLSI Adders," (pdf file)

*Proc. of the 1994 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 239-245, Oct. 1994.

[AlKo94] D. H. Albonesi and I. Koren, "Tradeoffs in the Design of Single Chip Multiprocessors," (pdf file)

*Proc. of the 1994 IFIP WG 10.3 Workshop on Parallel Architectures And Compilation Techniques*(PACT'94), pp. 25-34, Montreal, Canada, August 1994.

[LeKo94] R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, "The HYETI Defect Tolerant Microprocessor: A Practical Experiment and a Cost-Effectiveness Analysis," (pdf file)

*IEEE Trans. on Computers*, Vol. 43, pp. 1398-1406, Dec. 1994.

[KKSt94] I. Koren, Z. Koren and C.H. Stapper, "A Statistical Study of Defect Maps of Large Area VLSI ICs," (pdf file)

*IEEE Trans. on VLSI Systems*, Vol. 2, pp. 249-256, June 1994.

[PhKo94] D.S. Phatak and I. Koren, "Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains," (pdf file)

*IEEE Trans. on Computers*, Special Issue on Computer Arithmetic, Vol. 43, pp. 880-891, August 1994.

[PhKo94a] D.S. Phatak and I. Koren, "Connectivity and Performance Tradeoffs in the Cascade Correlation Learning Architecture," (pdf file)

*IEEE Trans. on Neural Nets,*Vol. 5, pp. 930-935, Nov. 1994.

[DaKo94] A. Dasgupta and I. Koren, "An Algorithm for Area and Delay Optimization of Sequential Machines through Decomposition," (pdf file)

*Proc. of HICSS-27, Hawaii Internl. Conf. on System Sciences,*vol. I, pp.36-45, Jan. 1994.

[PKC93] D.S. Phatak, I. Koren and H. Choi, "Hybrid Number Representations with Bounded Carry Propagation Chains," (pdf file)

*Proc. of ICCD'93 - the Internl. Conf. on Computer Design,*pp. 272-275, Oct. 1993.

[PCKo93] D.S. Phatak, H. Choi and I. Koren, "Construction of Minimal n-2-n Encoders for any n," (pdf file)

*Neural Computation,*no. 5, pp. 783-794, 1993.

[ChiKo93] V.K.R. Chiluvuri and I. Koren, "Topological Optimization of PLAs for Yield Enhancement," (pdf file)

*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 175-182, October 1993.

[ERKo93] D. Eisig, J. Rotstain and I. Koren, "The Design of a 64-bit Integer Multiplier/Divider Unit," (pdf file)

*Proc. of the 11th IEEE Symp. on Computer Arithmetic*, pp. 171-178, June 1993.

[KoKo93] Z. Koren and I. Koren, "Does the Floorplan of a Chip Affect Its Yield?" (pdf file)

*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 159-166, October 1993.

[WaKo93] I. A. Wagner and I. Koren, "An Interactive Yield Estimator as a VLSI CAD tool," (pdf file)

*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 167-174, October 1993.

[MeKo93] B. Mendelson and I. Koren, "Mapping Algorithms onto a Multiple-Chip Data-Driven Array," (pdf file)

*Proc. of ASAP 93 - the Internl. Conference on Application-Specific Array Processors,*pp. 41-52, October 1993.

[KKSt93] I. Koren, Z. Koren and C.H. Stapper, "A Unified Negative Binomial Distribution for Yield Analysis of Defect Tolerant Circuits," (pdf file)

*IEEE Trans. on Computers*, Vol. 42, pp. 724-437, June 1993.

[WKC93] S. Wimer, I. Koren and I. Cederbaum, "On Paths with the Shortest Average Arc Length in Weighted Graphs," (pdf file)

*Discrete Applied Math.,*Vol. 45, pp. 169-179, 1993.

[CKW92] I. Cederbaum, I. Koren and S. Wimer, "Balanced Block Spacing for VLSI Layout," (pdf file)

*Discrete Applied Mathematics,*Vol. 40, Special Issue on "Graphs and Electrical Engineering," pp. 303-318, 1992.

[PhKo92] D.S. Phatak and I. Koren, "Fault Tolerance of Feedforward Neural Nets for Classification Tasks," (pdf file)

*Proc. of the IEEE International Joint Conf. on Neural Networks,*pp. II.386-II.391, June 1992.

[KoKS92] I. Koren, Z. Koren and C.H. Stapper, "Analysis of Defect Maps of Large Area VLSI ICs," (pdf file)

*Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 267-276, November 1992.

[MeKo92] B. Mendelson and I. Koren, "Estimating the Potential Parallelism and Pipelining of Algorithms for Data Flow Machines," (pdf file)

*Journal of Parallel and Distributed Computing,*pp. 15-28, Jan. 1992.

[LZGK92] P. Lalwaney, L. Zenou, A. Ganz and I. Koren, "Optical Interconnects for Multiprocessors: Cost Performance Trade-Offs," (pdf file)

*Proc. of Frontiers '92: Symp. on The Frontiers of Massively Parallel Computation,*pp. 278-285, Oct. 1992.

[ChKo92] V.K.R. Chiluvuri and I. Koren, "Reliability Analysis of a Highly Integrated Multiprocessor System," (pdf file)

*Proc. of the IEEE Workshop on Fault Tolerant Parallel and Distributed Systems,*pp. 54-61, July 1992.

[ChKo92a] V.K.R. Chiluvuri and I. Koren, "New Routing and Compaction Strategies for Yield Enhancement," (pdf file

*Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 325-334, November 1992.

[ChKo92] W. Che and I. Koren, "Fault Spectrum Analysis for Fast Spare Allocation in Reconfigurable Arrays," (pdf file)

*Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 60-69, November 1992.

[PPK91] B. Patel, D. K. Pradhan and I. Koren, "High Level Synthesis of Data Driven ASICs," (pdf file)

*Proc. of ASIC91, IEEE Internl. Application-Specific ICs Conf.,*pp. 13-3.1-3.4, Sept. 1991.

[SKK91] D. Sitaram, I. Koren and C.M. Krishna, "A Random, Distributed Algorithm to Embed Trees in Partially Faulty Processor Arrays," (pdf file)

*Journal of Parallel and Distributed Computing,*Vol. 12, pp. 1-11, May 1991.

[MPK91] B. Mendelson, B. Patel and I. Koren, "Designing Special-purpose Co-processors Using the Data Flow Paradigm," (pdf file)

*Advanced Topics in Data Flow Computing,*L. Bic and J-L. Gaudiot (eds.), Ch. 21, pp. 547-570, Prentice-Hall, 1991.

[MeKo91] B. Mendelson and I. Koren, "Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays," (pdf file)

*Proc. of the 1991 Internl. Conf. on Parallel Processing,*pp. I.123-127, August 1991.

[KoKo91] Z. Koren and I. Koren, "A Model for Enhanced Manufacturability of Defect Tolerant Integrated Circuits," (pdf file)

*Proc. of the 1991 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems,*pp. 81-92, November 1991.

[KoKo91] I. Koren and Z. Koren, "Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems," (pdf file)

*IEEE Trans. on Computers*, pp. 1024-1033, Vol. 40, Sept. 1991.

[KoZi90] I. Koren and O. Zinaty, "Evaluating Elementary Functions in a Numerical Co-Processor Based on Rational Approximations," (pdf file)

*IEEE Trans. on Computers*, Special Issue on Computer Arithmetic, Vol. 39, pp. 1030-1037, August 1990.

[KoSi90] I. Koren and A.D. Singh, "Fault Tolerance in VLSI Circuits," (pdf file)

*Computer*, Special Issue on Fault-Tolerant Systems, Vol. 23, pp. 73-83, July 1990.

[KoKo90] I. Koren and Z. Koren, "A Unified Approach for Yield Analysis of Defect Tolerant Circuits," (pdf file)

*Defect and Fault Tolerance in VLSI Systems,*Vol. 2, C.H. Stapper, V.K. Jain and G. Saucier (eds.), pp. 33-45, Plenum, 1990.

[KKS90] I. Koren, Z. Koren and C. H. Stapper, "Employing the Unified Negative Binomial Distribution for Yield Analysis of Empirical Data," (pdf file)

*Proc. of the 1990 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, Nov. 1990.

[ShKo89] J-J. Shen and I. Koren, "Yield Enhancement Designs for WSI Cube Connected Cycles," (pdf file

*Proc. of Internl. Conf. on Wafer Scale Integration*, pp. 289-298, Jan. 1989.

[FK89] J.A. Feldman and I. Koren, "On Generating Two Dimensional CMOS Cells," (pdf file

*Proc. of the IEEE Int'l Conf. on CAD/CAM,*Dec. 1989.

[KK89] I. Koren and Z. Koren, "On Gracefully Degrading Multi-processors with Multi-stage Interconnection Networks," (pdf file)

*IEEE Trans. on Reliability,*Special Issue on "Reliability of Parallel and Distributed Computing Networks," Vol. 38, pp. 82-89, April 1989.

[KoSt89] I. Koren and C.H. Stapper, "Yield Models for Defect Tolerant VLSI Circuits: A Review," (pdf file)

*Defect and Fault Tolerance in VLSI Systems*, Vol. 1, I. Koren (ed.), pp. 1-21, Plenum, 1989. (Reprints of this and five other papers in this list appear in

*Manufacturing Yield Evaluation of VLSI/WSI Systems*, B. Ciciani (editor), IEEE Computer Society Press, Los Alamitos, 1995.)

[WKCe89] S. Wimer, I. Koren and I. Cederbaum, "Optimal Aspect Ratios of Building Blocks in VLSI," (pdf file)

*IEEE Trans. on Computer-Aided Design,*Vol. 8, pp. 139-145, Feb. 1989.

[KK89a] I. Koren and Z. Koren, "Discrete and Continuous Models for the Performance of Multi-stage Systems in the Presence of Faulty Components," (pdf file

*Proc. of HICSS-22, Hawaii Internl. Conf. on System Sciences,*pp. 724-732, Jan. 1989.

[KMPS88] I. Koren, B. Mendelson, I. Peled and G.M. Silberman, "A Data-Driven VLSI Array for Arbitrary Algorithms," (pdf file)

*Computer*, Vol. 21, pp. 30-43, October 1988.

[KK88] I. Koren and Z. Koren, "Analyzing the Connectivity and Bandwidth of Multi-processors with Multi-stage Interconnection Networks," (pdf file )

*Concurrent Computations: Algorithms, Architecture and Technology,*S.K. Tewksbury, B.W. Dickinson and S.C. Schwartz (eds.), Chapter 26, pp. 525-540, Plenum, 1988.

[WKCe88] S. Wimer, I. Koren and I. Cederbaum, "Floorplans, Planar Graphs and Layouts," (pdf file)

*IEEE Trans. on Circuits and Systems*, Special Issue on "Computational Graph Theory: Algorithms and Applications," Vol. 35, pp. 267-278, March 1988.

[KKP88] I. Koren, Z. Koren and D.K. Pradhan, "Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay," (pdf file)

*IEEE Journal of Solid-state Circuits,*Vol. 23, pp. 859-866, Mar. 1988.

[KK88] I. Koren and Z. Koren, "On the Bandwidth of a Multi-stage Network in the Presence of Faulty Components," (pdf file)

*Proc. of the 8th Internl. Conf. on Distributed Computing Systems,*pp. 26-32, June 1988.

[Koren88] I. Koren, "The Effect of Scaling on the Yield of VLSI Circuits," (pdf file)

*Yield Modelling and Defect Tolerance in VLSI*, W.R. Moore, W. Maly and A. Strojwas (Eds.), pp. 91-99, Adam Hillger Ltd., 1988.

[WiKo88] S. Wimer and I. Koren, "Analysis of Strategies for Constructive General Block Placement," (pdf file)

*IEEE Trans. on Computer-Aided Design*, Vol. 7, pp. 371-377, March 1988.

[ErKo88] P. Erdos, I. Koren, S. Moran, G.M. Silberman and S. Zaks, "Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays," (pdf file)

*Mathematical Systems Theory,*Vol. 21, No. 2, pp. 85-98, 1988.

See here the list of holders of Paul Erdos numbers.

[WKC88] Wimer, I. Koren and I. Cederbaum, "Optimal Aspect Ratios of Building Blocks in VLSI," (pdf file)

*Proc. of the 25th Design Automation Conf.,*pp. 66-72, June 1988.

[GoKS87] D. Gordon, I. Koren and G.M. Silberman, "Restructuring Hexagonal Arrays of Processors in the Presence of Faults," (pdf file)

*Journal of VLSI and Computer Systems,*Vol. 2, No. 1, pp. 23-35, 1987.

[GrKS87] M. Granski, I. Koren, and G.M. Silberman, "The Effect of Operations Scheduling on the Performance of Data Flow Computers," (pdf file)

*IEEE Trans. on Computers,*Vol. C-36, pp. 1019-1029, Sept. 1987.

[KoPo87] I. Koren and I. Pomeranz, "Distributed Structuring of Processor Arrays in the Presence of Faulty Processors," (pdf file)

*Systolic Arrays,*W.R. Moore, A. McCabe and R. Urquhart (Eds.), pp. 239-248, Adam Hillger Ltd., 1987.

[KP87] I. Koren and D.K. Pradhan, "Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems," (pdf file)

*IEEE Trans. on Computers,*Vol. C-36, pp. 344-355, Mar. 1987.

[KKP87] I. Koren, Z. Koren and D.K. Pradhan, "Wafer-Scale Integration of Multi-processor Systems," (pdf file)

*Proc. of HICSS-20, Hawaii Internl. Conf. on System Sciences,*pp. 13-20, Jan. 1987.

[BeKo87] M. Berg and I. Koren, "On Switching Policies for Modular Fault-Tolerant Computing Systems," (pdf file)

*IEEE Trans. on Computers,*Vol. C-36, pp. 1052-1062, Sept. 1987.

[KP87] I. Koren and I. Peled, "A "The Concept and Implementation of Data-Driven Processor Arrays," (pdf file)

*Computer,*Vol. 20, pp.102-103, July 1987.

[WK86] S. Wimer and I. Koren, "Constructive Placement of General Blocks in VLSI under Uncertainties in the Position of Ports," (pdf file)

*Proc. of the 1986 Internl. Conf. on Computer--Aided Design,*4pp., Nov. 1986.

[KP86] I. Koren and D.K. Pradhan, "Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-processor Systems," (pdf file)

*Proc. of IEEE,*Vol. 74, pp. 699-711, May 1986.

[KKS86] I. Koren Z. Koren and S.Y.H. Su, "Analysis of a Class of Recovery Procedures," (pdf file)

*IEEE Trans. on Computers,*Vol. C-35, pp. 703-712, August 1986.

[KoPr85] I. Koren and D.K. Pradhan, "Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement," (pdf file

*Proc. of the 15th Internl. Symp. on Fault-Tolerant Computing*, pp. 330-335, June 1985.

[MiKo85] Mizhrahi and I. Koren, "Evaluating the Cost-Effectiveness of Switches in Processor Arrays Architectures," (pdf file)

*Proc. of the 1985 Internl. Conf. on Parallel Processing,*pp. 480-487, August 1985.

[KB84] I. Koren and M. A. Breuer, "On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays," (pdf file)

*IEEE Trans. on Computers,*Vol. C-33, pp. 21-27, Jan. 1984.

[KoSh84] I. Koren and E. Shalev, "Reliability Analysis of Hybrid Redundancy Systems," (pdf file)

*IEE Proc., Computer and Digital Techniques,*Vol. 131, No. 1, pp. 31-36, January 1984.

[GKS84] D. Gordon, I. Koren and G.M. Silberman, "Embedding Tree Structures in VLSI Hexagonal Arrays," (pdf file)

*IEEE Trans. on Computers,*Vol. C-33, pp. 104-107, Jan. 1984.

[KS83] I. Koren and G.M. Silberman, "A Direct Mapping of Algorithms onto VLSI Processor Arrays Based on the Data Flow Approach," (pdf file)

*Proc. of the 1983 Internl. Conf. on Parallel Processing,*pp. 335-337, August 1983.

[AlKo82] D. Aljadeff and I. Koren, "A Microprocessor-based Hardware Monitor for Performance Evaluation of Computer Systems," (pdf file)

*Microsystems: Architecture and Integration, EUROMICRO 82,*C.J. van Spronsen and L. Richter (eds.), North-Holland, pp. 123-130, 1982.

[KoMa81] I. Koren and Y. Maliniak, "On Classes of Positive, Negative and Imaginary Radix Number Systems," (pdf file)

*IEEE Trans. on Computers,*Vol. C-30, pp. 312-317, May 1981.

[KoBe81] I. Koren and M. Berg, "A Module Replacement Policy for Dynamic Fault-Tolerant Computing Systems," (pdf file)

*Proc. of the 11th Internl. Symp. on Fault-Tolerant Computing,*pp. 90-95, June 1981.

[Kore81] I. Koren, "A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array," (pdf file)

*Proc. of the 8th Annual Symp. on Computer Architecture*, pp. 425-441, May 1981.

[KoSa80] I. Koren and E. Sadeh, "A New Approach to the Evaluation of the Reliability of Digital Systems," (pdf file)

*IEEE Trans. on Computers,*Vol. C-29, pp. 261-267, March 1980.

[KoSa80a] I. Koren and E. Sadeh, "On the Convergence of the Signal Reliability of Iterative and Sequential Systems," (pdf file)

*Digital Processes,*6, pp. 21-33, 1980.

[Kore79] I. Koren, "Analysis of the Signal Reliability Measure and an Evaluation Procedure," (pdf file)

*IEEE Trans. on Computers,*Vol. C-28, pp. 244-249, March 1979.

[KoKo79] I. Koren and Z. Kohavi, "On the Properties of Sensitized Paths," (pdf file)

*IEEE Trans. on Computers,*Vol. C-28, pp. 268-269, March 1979.

[KoSu79] I. Koren and S.Y.H. Su, "Reliability Analysis of N-Modular Systems with Intermittent and Permanent Faults," (pdf file)

*IEEE Trans. on Comp.,*Vol. C-28, pp. 514-520, July 1979.

[KoMa78] I. Koren and Y. Maliniak, "A Unified Approach to a Class of Number Systems," (pdf file)

*Proc. of the 4th IEEE Symp. on Computer Arithmetic,*pp. 25-28, October 1978.

[skm78] S.Y.H. Su, I. Koren and Y.K. Malaiya, "A Continuous Parameter Markov Model and Detection Procedures for Intermittent Faults," (pdf file)

*IEEE Trans. on Computers,*Vol. C-27, pp. 567-570, June 1978.

[Kore77] I. Koren, "Signal Reliability of Combinational and Sequential Circuits," (pdf file)

*Proc. of the 7th Internl. Symp. on Fault-Tolerant Computing,*pp. 162-177, June 1977.

[KoKo77] I. Koren and Z. Kohavi, "Sequential Fault Diagnosis in Combinational Networks," (pdf file)

*IEEE Trans. on Computers,*Vol. C-26, pp. 334-342, April 1977.

[KoKo77a] I. Koren and Z. Kohavi, "Diagnosis of Intermittent Faults in Combinational Networks," (pdf file)

*IEEE Trans. on Computers,*Vol.C-26, pp. 1154-1158, Nov. 1977.

[KoKo76] I. Koren and Z. Kohavi, "Adaptive Fault Locating Tests for Digital Systems," (pdf file)

*Digital Processes,*vol. 2, 3, pp. 209-223, 1976.

*Israel Koren*

koren 'at' euler.ecs.umass.edu

koren 'at' euler.ecs.umass.edu