• Z. Zhang, B. Madabhushi, S, Kundu, and R. Tessier, Managing Computation Offloading from Edge Devices to a Reconfigurable Edge Cloud, in the Proceedings of the IEEE Conference on Application-specific Systems, Architectures, and Processors, Vancouver, BC, July 2025. 
  
• B. Madabhushi, Z. Zhang, T. Alves, R. Tessier, and S. Kundu, Efficient Onboard SAR Image Processing for Real-Time Ship Detection and Data Reduction, in the Proceedings of the OCEANS Conference and Exhibition, Halifax, NS, September 2024. 
  
• Z. Zhang, B. Madabhushi, S. Kundu, and R. Tessier, Security Risks Due to Data Persistence in Cloud FPGA Platforms, in the Proceedings of the Midwest Symposium on Circuits and Systems, Springfield, MA, August 2024. 
  
• D. Gnad, M. Gotthard, J. Krautter, A. Kritikakou, V. Meyers, P. Rech, J. Condia, A. Ruospo, E. Sanchez, F. dos Santos, O. Sentieys, M. Tahoori, R. Tessier, and M. Traiola, Reliability and Security of AI Hardware, in the Proceedings of the European Test Symposium, The Hague, Netherlands, May 2024. 
  
• S. Moini, D. Kansagara, D. Holcomb, and R. Tessier, Fault Recovery from Multi-Tenant FPGA Voltage Attacks, in the Proceedings of the ACM Great Lakes Symposium on VLSI, Knoxville, TN, June 2023. 
  
• M. El Bouazzati, R. Tessier, P. Tanguy, and G. Gogniat, Lightweight Intrusion Detection System against IoT Memory Corruption Attacks, in the Proceedings of the International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallinn, Estonia, May 2023. 
  
• S. Tian, S. Moini, D. Holcomb, R. Tessier, and J. Szefer, A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Antwerp, Belgium, April 2023. 
  
• X. Li, R. Tessier and D. Holcomb, Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, virtual conference, May 2022. 
  
• N. Albartus, C. Nasenberg, F. Stoltz, C. Paar, and R. Tessier, On the Design and Misuse of Microcoded (Embedded) Processors - A Cautionary Note, in the Proceedings of the 30th Usenix Security Symposium, virtual conference, August 2021. 
  
• T. Wolf, R. Tessier, Y. Eslami, C. Hollot, and B. Polivka, Challenges and Successes in Synchronous Cohort-Based International Education, in the Proceedings of the ASEE Annual Conference and Exposition, virtual conference, July 2021. 
  
• S. Tian, S. Moini, A. Wolnikowski, D. Holcomb, R. Tessier and J. Szefer, Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, virtual conference, May 2021. 
  
• S. Moini, S. Tian, D. Holcomb, J. Szefer, and R. Tessier, Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, virtual conference, February 2021. 
  
• X. Li, P. Stanwicks, G. Provelengios, R. Tessier, and D. Holcomb, Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud, in the Proceedings of the International Conference on Field-Programmable Technology, virtual conference, December 2020. 
  
• X. Zhang and R. Tessier, Service Chaining for Heterogeneous Middleboxes, in the Proceedings of the International Conference on Field-Programmable Technology, virtual conference, December 2020. 
  
• X. Zhang, N. Prabhu, and R. Tessier, NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks, in the Proceeding of the 31st IEEE International Workshop on Rapid Systems Prototyping, virtual conference, October 2020. 
  
• G. Provelengios, D. Holcomb, and R. Tessier, Power Wasting Circuits for Cloud FPGA Attacks, in the Proceedings of the International Conference on Field Programmable Logic and Applications, virtual conference, September 2020. 
  
• S. Moini, X. Li, P. Stanwicks, G. Provelengios, W. Burleson, R. Tessier, and D. Holcomb, Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs, in the Proceedings of the Midwest Symposium on Circuits and Systems, virtual conference, August 2020. 
  
• T. Wolf, C. Hollot, R. Tessier, B. Polivka, and Y. Eslami, Scalable Synchronous Cohort-based International Education, in the Proceedings of the ASEE Annual Conference and Exposition, virtual conference, June 2020. 
  
• G. Provelengios, D. Holcomb, and R. Tessier, Characterizing Power Distribution Attacks in Multi-User FPGA Environments, in the Proceedings of the International Conference on Field Programmable Logic and Applications, Barcelona, Spain, September 2019. 
  
• T. Wolf, C. Hollot, R. Tessier, B. Polivka, C. Hoehn-Saric, J. Kang, and K. Newman, Synchronous Cohort-Based International Education, in the Proceedings of the ASEE Annual Conference and Exposition, Tampa, FL, June 2019. 
  
• L. Xia, A. Soltan, X. Zhang, A. Jackson, R. Tessier and P. Degenaar, Closed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model, in the Proceedings of the IEEE International Conference on Circuits and Systems, Sapporo, Japan, May 2019. 
  
• G. Provelengios, C. Ramesh, S. B. Patil, K. Eguro, R. Tessier, and D. Holcomb, Characterization of Long Wire Data Leakage in Deep Submicron FPGAs, in the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Seaside, CA, February 2019. 
  
• J. Dechelotte, D. Dallet, J. Crenne, and R. Tessier, Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, Dublin, Ireland, August 2018. 
  
• G. Provelengios, A. Pouraghily, R. Tessier, and T. Wolf, A Hardware Monitor to Protect Linux System Calls, in the Proceedings of the IEEE International Symposium on VLSI, Hong Kong, China, July 2018. 
  
• C. Ramesh, S. B. Patil, S. N. Dhanuskodi, G. Provelengios, S. Pillement, D. Holcomb, and R. Tessier, FPGA Side Channel Attacks without Physical Access, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, May 2018. 
  
• S. B. Patil, T. Liu, and R. Tessier, A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Boulder, CO, May 2018. 
  
• V. Migliore, C. Seguin, M. M. Real, V. Lapotra, A. Tisserand, C. Fontaine, G. Gogniat, and R. Tessier, A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm, in the Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, Seoul, South Korea, October 2017. 
  
• A. Pouraghily, T. Wolf, and R. Tessier, Hardware Support for Embedded Operating System Security, in the Proceedings of the IEEE Conference on Application-specific Systems, Architectures, and Processors, Seattle, WA, July 2017. 
  
• X. Zhang, X. Shao, G. Provelengios, N. Dumpala, L. Gao, and R. Tessier, Scalable Network Function Virtualization for Heterogeneous Middleboxes, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, May 2017. 
  
• N. Dumpala, S. B. Patil, D. Holcomb, and R. Tessier, Energy Efficient Loop Unrolling for Low-Cost FPGAs, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, May 2017. 
  
• T. Liu, N. Dumpala, and R. Tessier, Hybrid Hard NoCs for Efficient FPGA Communication, in the Proceedings of the International Conference on Field-Programmable Technology, Xi'an, China, December 2016. 
  
• C. Huriaux, O. Sentieys, and R. Tessier, Effects of I/O Routing through Column Interfaces in Embedded FPGA Fabrics, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland, September 2016. 
  
• S. Vyas, N. Dumpala, R. Tessier, and D. Holcomb, Improving the Efficiency of PUF-Based Key Generation in FPGAs Using Variation-Aware Placement, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland, September 2016. 
  
• K. Andryc, T. Thomas, and R. Tessier, Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation, in the Proceedings of the Second Workshop on Overlay Architectures for FPGAs, Monterey, CA, February 2016. 
  
• X. Liu, T. Thomas, A. Boguslawski, and R. Tessier, Adaptive MRAM-Based CGRAs, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, London, England, September 2015. 
  
• T. Thomas, A. Pouraghily, K. Hu, R. Tessier, and T. Wolf, Multi-Task Support for Security-Enabled Embedded Processors, in the Proceedings of the IEEE Conference on Application-specific Systems, Architectures, and Processors, Toronto, ON, Canada, July 2015. 
  
• J. Lu, R. Tessier, and W. Burleson, Reinforcement Learning For Thermal-Aware Many-Core Task Allocation, in the Proceedings of the ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, May 2015. 
  
• P. Swierczynski, M. Fyrbiak, C. Paar, C. Huriaux, and R. Tessier, Protecting against Cryptographic Trojans in FPGAs, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Vancouver, British Columbia, May 2015. 
  
• M. Kainth, L. Krishnan, C. Narayana, S. Virupaksha, and R. Tessier, Hardware-Assisted Code Obfuscation for FPGA Soft Microprocessors, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Grenoble, France, March 2015. 
  
• C. Huriaux, O. Sentieys, and R. Tessier, FPGA Architecture Support for Heterogeneous, Relocatable Partial Bitstreams, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, Munich, Germany, September 2014. 
  
• J. Zhao, J. Lu, W. Burleson, and R. Tessier, A Broadcast-Enabled Sensing System for Embedded Multi-core Processors, in the Proceedings of the IEEE International Symposium on VLSI, Tampa, FL, July 2014. 
  
• K. Hu, T. Wolf, T. Teixeira, and R. Tessier, System-Level Security for Network Processors with Hardware Monitors, in the Proceedings of the IEEE/ACM Design Automation Conference, San Francisco, CA, June 2014. 
  
• K. Andryc, M. Merchant, and R. Tessier, FlexGrip: A Soft GPGPU for FPGAs, in the Proceedings of the International Conference on Field-Programmable Technology, Kyoto, Japan, December 2013. 
  
• D. Unnikrishnan, S. Virupaksha, L. Krishnan, L. Gao, and R. Tessier, Accelerating Iterative Algorithms with Asynchronous Accumulative Updates on FPGAs, in the Proceedings of the International Conference on Field-Programmable Technology, Kyoto, Japan, December 2013. 
  
• C. Gorman, P. Siqueira, and R. Tessier, An Open-Source SATA Core for Virtex-4 FPGAs, in the Proceedings of the International Conference on Field-Programmable Technology, Kyoto, Japan, December 2013. 
  
• K. Hu, H. Chandrikakutty, R. Tessier, and T. Wolf, Scalable Hardware Monitors to Protect Network Processors from Data Plane Attacks, in the Proceedings of the IEEE International Conference on Communications and Network Security, Washington, DC, October 2013. 
  
• H. Chandrikakutty, D. Unnikrishnan, R. Tessier, and T. Wolf, High-Performance Hardware Monitors to Protect Network Processors from Data Plane Attacks, in the Proceedings of the IEEE/ACM Design Automation Conference, Austin, TX, June 2013. 
  
• K. Pocek, R. Tessier, and A. DeHon, Birth and Adolescence of Reconfigurable Computing: A Survey of the First 20 Years of Field-Programmable Custom Computing Machines, in the Highlights of the First Twenty Years of the IEEE International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, April 2013. 
  
• D. Gomez-Prado, M. Ciesielski, and R. Tessier, FPGA Latency Optimization Using System-level Transformations and DFG Restructuring, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Grenoble, France, March 2013. 
  
• J. Zhao, J. Lu, W. Burleson and R. Tessier, Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Grenoble, France, March 2013. 
  
• J. Lu, R. Tessier and W. Burleson, Collaborative Calibration of On-Chip Thermal Sensors Using Performance Counters, in the Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, November 2012. 
  
• Y. S. Hanay, W. Li, R. Tessier, and T. Wolf, Saving Energy and Improving TCP Throughput with Rate Adaptation in Ethernet, in the Proceedings of the IEEE International Conference on Communications, Ottawa, Ontario, Canada, June 2012. 
  
• J. Zhao, R. Tessier, and W. Burleson, Distributed Sensor Data Processing for Many-cores, in the Proceedings of the ACM Great Lakes Symposium on VLSI, Salt Lake City, Utah, May 2012. 
  
• J. Crenne, P. Cotret, G. Gogniat, R. Tessier, and J.-P. Diguet, Efficient Key-Dependent Message Authentication in Reconfigurable Hardware, in the Proceedings of the IEEE International Conference on Field-Programmable Technology, New Delhi, India, December 2011. 
  
• D. Unnikrishnan, J. Lu, L. Gao, and R. Tessier, ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization, in the Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, Brooklyn, NY, October 2011. 
  
• E. Seguin, R. Tessier, E. Knapp, and R. W. Jackson, A Dynamically-Reconfigurable Phased Array Radar Processing System, in the Proceedings of the International Conference on Field-Programmable Logic and Applications, Chania, Greece, September 2011. 
  
• B. Bovee, M. Nekoui, H. Pishro-Nik, and R. Tessier, Evaluation of the Universal Geocast Scheme For VANETs, in the Proceedings of the IEEE Vehicular Technology Conference, San Francisco, CA, September 2011. 
  
• V. Vijayendra, P. Siqueira, H. Chandrikakutty, A. Krishnamurthy, and R. Tessier, Real-Time Estimates of Differential Signal Phase for Spaceborne Systems Using FPGAs, in the Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, San Diego, CA, June 2011. 
  
• D. Yin, D. Unnikrishnan, Y. Liao, L. Gao, and R. Tessier, Customizing Virtual Networks with Partial FPGA Reconfiguration, in the Proceedings of the ACM SIGCOMM Workshop on Virtualized Infrastructure Systems and Architectures, New Delhi, India, August 2010. 
  
• J. Zhao, B. Datta, W. Burleson and R. Tessier, Thermal-aware Voltage Droop Compensation for Multi-core Architectures, in the Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, Providence, RI, May 2010. 
  
• R. Vadlamani, J. Zhao, W. Burleson and R. Tessier, Multicore Soft Error Rate Stabilization Using Adaptive Dual Modular Redundancy, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Dresden, Germany, March 2010. 
  
• D. Unnikrishnan, R. Vadlamani, Y. Liao, A. Dwaraki, J. Crenne, L. Gao, and R. Tessier, Scalable Network Virtualization Using FPGAs, in the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2010. 
  
• T. Wolf and R. Tessier, Design of a Secure Router System for Next-Generation Networks, in the Proceedings of the IEEE International Conference on Network and System Security, Gold Coast, Australia, October 2009. 
  
• K. Andryc, R. Tessier, and P. Kelly, An Interactive Approach to Timing-Accurate PCI-X Simulation, in the Proceedings of the IEEE/IFIP International Symposium on Rapid Systems Prototyping, Paris, France, June 2009. 
  
• S. Madduri, R. Vadlamani, W. Burleson and R. Tessier, A Monitor Interconnect and Support Subsystem for Multicore Processors, in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, Nice, France, April 2009. 
  
• D. Unnikrishnan, J. Zhao and R. Tessier, Application-Specific Customization and Scalability of Soft Multiprocessors, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2009. 
  
• R. Vaslin, G. Gogniat, J.-P. Diguet, R. Tessier, D. Unnikrishnan, and K. Gaj, Memory Security Management for Reconfigurable Embedded Systems, in the Proceedings of the IEEE International Conference on Field-Programmable Technology, Taipai, Taiwan, December 2008. 
  
• D. Howland and R. Tessier, RTL Dynamic Power Optimization for FPGAs, in the Proceedings of the IEEE Midwest Symposium on Circuits and Systems, Nashville, TN, August 2008. 
  
• W. Xu and R. Tessier, Tetris: A New Register Pressure Control Technique for VLIW Processors, in the Proceedings of the ACM/SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, San Diego, CA, June 2007. 
  
• K. Tinmaung, D. Howland, and R. Tessier, Power-aware FPGA Logic Synthesis Using Binary Decision Diagrams, in the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2007. 
  
• R. Tessier, V. Betz, D. Neto, and T. Gopalsamy, Power-aware RAM Mapping for FPGA Embedded Memory Blocks, in the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2006. 
  
• L. Atieno, J. Allen, D. Goeckel, and R. Tessier, An Adaptive Reed-Solomon Errors-and-Erasures Decoder, in the Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2006. 
  
• R. Khasgiwale, L. Krnan, A. Perinkulam, and R. Tessier, Reconfigurable Data Acquisition System for Weather Radar Applications, in the Proceedings of the IEEE Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, August 2005. 
  
• D. Perkovic, S. Frasier, R. Tessier, M. Sletten, and J. Toporkov, An Airborne, Pod-mounted Dual Beam Interferometer, in the Proceedings of IEEE Aerospace Conference, Big Sky, Montana, March 2005. 
  
• J. Liang, R. Tessier, and D. Goeckel, A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2004. 
  
• A. Laffely, J. Liang, R. Tessier, and W. Burleson, Adaptive System on a Chip: A Backbone for Power-Aware Signal Processing Cores, Proceedings of the IEEE Conference on Image Processing, Barcelona, Spain, September 2003. 
  
• W. Xu, R. Ramanarayanan, and R. Tessier, Adaptive Fault Tolerance for Networked Reconfigurable Systems, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2003. 
  
• J. Liang, R. Tessier, and O. Mencer, Floating Point Unit Generation and Evaluation for FPGAs, in the Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2003. 
  
• A. Natarajan, D. Jasinski, W. Burleson, and R. Tessier, A Hybrid Adiabatic Content Addressable Memory for Ultra-Low Power Applications, in the Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, Washington, D.C., April 2003. 
  
• R. Ramaswamy and R. Tessier, The Integration of SystemC and Hardware-assisted Verification, in the Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, Montpelier, France. September 2002. 
  
• A. Maheshwari, W. Burleson and R. Tessier, Trading Off Reliability and Power Consumption in Ultra-Low Power Systems, in the Proceedings of the International Symposium on Quality Electronic Design, San Jose, California, March 2002. 
  
• S. Swaminathan, R. Tessier, D. Goeckel, and W. Burleson, A Dynamically Reconfigurable Adaptive Viterbi Decoder, in the Proceedings of the 10th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, California, February 2002. 
  
• A. Laffely, J. Liang, P. Jain, N. Weng, W. Burleson and R. Tessier, Adaptive Systems on a Chip (aSoC) for Low-Power Signal Processing, in the Proceedings of the Asilomar Conference on Signals, Systems, and Computers, Monterey, California, November 2001. 
  
• M. Kudlugi, C. Selvidge, and R. Tessier, Static Scheduling of Multi-Domain Memories for Functional Verification, in the Proceedings of the International Conference on Computer Aided Design, San Jose, California, November 2001. 
  
• I. G. Harris, P. Menon, and R. Tessier, BIST-Based Delay Path Testing in FPGA Architectures, in the Proceedings of the International Test Conference, Baltimore, Maryland, October 2001. 
  
• M. Kudlugi, C. Selvidge, and R. Tessier, Static Scheduling of Multiple Asynchronous Domains for Functional Verification, in the Proceedings of the 38th Design Automation Conference, Las Vegas, Nevada, June 2001. 
  
• M. Kudlugi and R. Tessier, Multi-domain Communication for FPGA-based Logic Emulation, in the Proceedings of the 10th International Workshop on Logic and Synthesis, Lake Tahoe, Nevada, June 2001. 
  
• M. Singh, S. Thampuran, P. Jain, R. Tessier, C. A. Moritz, Short Range Wireless Connectivity for Next Generation Architectures, in the Proceedings of the 2001 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'2001) , Las Vegas, Nevada, June 2001. 
  
• W. Burleson, R. Tessier, D. Goeckel, S. Swaminathan, P. Jain, J. Euh, S. Venkatraman and V. Thyagarajan, Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power, in the Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, 2001 (ICASSP'01). Salt Lake City, Utah, May 2001. 
  
• I. G. Harris and R. Tessier, Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures, in the Proceedings of the International Conference on Computer Aided Design, San Jose, California, November 2000.  
  
• J. Liang, S. Swaminathan, and R. Tessier, aSOC: A Scalable, Single-Chip Communications Architecture, in the Proceedings of the IEEE International Conference on Parallel Architectures and Compilation Techniques, Philadelphia, PA. October 2000.  
  
• R. Tessier and H. Giza, Balancing Logic Utilization and Area Efficiency in FPGAs, in the Proceedings of the 10th International Conference on Field-Programmable Logic and Applications, Villach, Austria. August 2000.  
  
• S. Krishnamoorthy, S. Swaminathan, and R. Tessier, Area-Optimized Technology Mapping for Hybrid FPGAs, in the Proceedings of the 10th International Conference on Field-Programmable Logic and Applications, Villach, Austria. August 2000.  
  
• I. G. Harris and R. Tessier, Interconnect Testing in Cluster-Based FPGA Architectures, in the Proceedings of the 37th Design Automation Conference, Los Angeles, California, June 2000.  
  
• V. Lakamraju and R. Tessier, Tolerating Operational Faults in Cluster-based FPGAs, in the Proceedings of the 8th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, California, February 2000.  
  
• R. Tessier, Frontier: A Fast Placement System for FPGAs, in the Proceedings of the Tenth IFIP International Conference on VLSI, Lisbon, Portugal, December 1999.  
  
• R. Tessier, Incremental Compilation for Logic Emulation, in the Proceeding of the 10th IEEE International Workshop on Rapid Systems Prototyping, Clearwater, Florida, June 1999.  
  
• R. Tessier, Negotiated A* Routing for FPGAs, in the Proceeding of the 5th Canadian Workshop on Field Programmable Devices, Montreal, Quebec, Canada, June 1998.  
  
• M. Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki, and A. Agarwal, Emulation of a Sparc Microprocessor with the MIT Virtual Wires Emulation System, in the Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 1994. 
  
• R. Tessier, J. Babb, M. Dahl, S. Hanano, and A. Agarwal, The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment, in the Proceedings of the 2nd International ACM/SIGDA Workshop on Field Programmable Gate Arrays, Berkeley, California, February 1994.  
  
• J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, in the Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa, California, April 1993.