Biography

Israel Koren received the B.Sc., M.Sc. and D.Sc. degrees from the Technion - Israel Institute of Technology, Haifa, in 1967, 1970, and 1975, respectively, all in Electrical Engineering. He is currently a Professor of Electrical and Computer Engineering at the University of Massachusetts, Amherst. Previously he held positions with the Technion - Israel Institute of Technology, Haifa, the University of California at Berkeley, the University of Southern California, Los Angeles and the University of California, Santa Barbara. He has been a consultant to several companies including Analog Devices, AMD, Digital Equipment Corp., IBM, Intel, National Semiconductor and Tolerant Systems.

Dr. Koren's current research interests are Fault-Tolerant Systems, VLSI Yield and Reliability, Secure Cryptographic Systems, and Computer Arithmetic. He publishes extensively and has over 250 publications in refereed journals and conferences. He is an Associate Editor of the VLSI Design Journal, and the IEEE Computer Architecture Letters. He has been a Co-Guest Editor for several IEEE Transactions on Computers special issues on Fault Diagnosis and Tolerance in Cryptography, Sept. 2006, on Computer Arithmetic, July 2000, and on High Yield VLSI Systems, April 1989. He served on the Editorial Board of these Transactions during 1992-1997, and on the Editorial Board of the IEEE Transactions on VLSI Systems during 2001-2006. He also served as General Chair, Program Chair and Program Committee member for numerous conferences. He has edited and co-authored the book, Defect and Fault-Tolerance in VLSI Systems, Vol. 1, Plenum, 1989. He is the author of the textbook Computer Arithmetic Algorithms, Second Edition, A. K. Peters, Natick, MA, 2002. He is a co-author of the textbook Fault-Tolerant Systems,, Morgan-Kaufman, San Francisco, CA, 2007. Dr. Koren is a Fellow of the IEEE.

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Research Interests

Research is being conducted in the following directions (the pointers in brackets indicate the relevant publications in the list below or follow the link to Prior Publications):

Multicore and SMT Architectures: [WKK11], [DRKK10], [WKK08].

Power and Temperature Aware Systems: [KoKr11], [HaKo07], [HKK07], [WGKK06], [GKK05], [UnKo03], [URKK01].

Secure Cryptogrpahic devices: [BPBKR10], [REBIK08], [ABPK07], [REGB07], [BNK07], [BBKMP03a], [BBKMP03b], [BBKMP03].

Fault-Tolerant Systems: [KoKr07], [ZLKK07], [UnKo03], [DuKK01], [HLKK00], [ACDH00], [KKKr98], [YuKo95].

Defect and fault tolerance [LCKK09], [ChKo04], [SiKo03], [KoKo00].

Digital computer arithmetic: [Kore02], [WoKo05], [KKO03], [PhGK01], [PhKo99].

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Selected List of Recent Publications (copyright note):

[KoKr07] Textbook: I. Koren and C. M. Krishna, Fault-Tolerant Systems,, Morgan-Kaufman, San Francisco, CA, 2007.

[Kore02] Textbook: I. Koren, Computer Arithmetic Algorithms, Second Edition, A. K. Peters, Natick, MA, 2002.

[BBKN12] A. Barenghi, L. Breveglieri, I. Koren and D. Naccache, "Fault Injection Attacks on Cryptographic Devices: Theory, Practice and Countermeasures," ( pdf file), Proceedings of the IEEE, April 2012.

[KoKr11] I. Koren and C. M. Krishna, "Temperature-Aware Computing," (Invited Paper), ( pdf file), Sustainable Computing: Informatics and Systems, Vol. 1, pp. 46-56, March 2011.

[ARKK12] A. Annamalai, R. Rodrigues, I. Koren and S. Kundu, "Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt," ( pdf file), Proc. of the 8th IEEE Workshop on High-Performance, Power-Aware Computing (HPPAC/IPDPS), May 2012.

[RKK11] R. Rodrigues, I. Koren and S. Kundu, "An Architecture to enable Life Cycle Testing of CMPs," ( pdf file), Proc. of the 2011 IEEE Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11), Oct. 2011.

[ARKK11] A. Annamalai, R. Rodrigues, I. Koren, S. Kundu and O. Khan, "Performance per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores," ( pdf file), Proc. of the 2011 IEEE Conf. on Parallel Architectures and Compilation Techniques (PACT'11), Oct. 2011.

[WKK11] H. Wang, I. Koren and C.M. Krishna, "Utilization-Based Resurce Partitioning for Power-Performance Efficiency in SMT Processors,"(pdf file), IEEE Trans. on Parallel and Distributed Systems, pp. 1150-1163, July 2011.

[SKNBKWM10] P. Shabadi, A. Khitun, P. Narayanan, M. Bao, I. Koren, K. L. Wang and C. A. Moritz, "Towards Logic Functions as the Device," (pdf file), Proc. of the 2010 IEEE/ACM Intern. Sympos. on NanoScale Architectures (NanoArch'10), June 2010.

[BPBKR10] A. Barenghi, G. Pelosi, L. Breveglieri, I. Koren and F. Regazzoni, ``Low-cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade offs," (pdf file), Proc. of the 5th workshop on Embedded Security, WESS'2010, Oct. 2010.

[DRKK10] A. Das, R. Rodrigues, I. Koren, and S. Kundu, ``A Study on the Performance Benefits of Core Morphing in an Asymmetric Multicore Processor," (pdf file), Proc. of the IEEE Internl. Conference on Computer Design, ICCD'10, Oct. 2010.

[SKKK09] S. Sundaresan, I. Koren, Z. Koren and C. M. Krishna, "Event-Driven Adaptive Duty-Cycling in Sensor Networks," (pdf file), International Journal of Sensor Networks (IJSNet), vol. 6, No. 2, pp. 89-100, 2009.

[LCKK09] J. Leung, G. Chapman, I. Koren, and Z. Koren, "Statistical Identification and Analysis of Defect Development in Digital Imagers," (pdf file), Proc. of the 21th SPIE Electronic Imaging Symposium, vol. 7250, pp. 7250W1-W12, Jan. 2009.

[REBIK08] F. Regazzoni, T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, "Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?" (pdf file), Proc. of the 2008 IEEE Intern. Sympos. on Defect and Fault Tolerance in VLSI Systems, Oct. 2008.

[WKK08] H. Wang, I. Koren and C. M. Krishna, "An Adaptive Resource Partitioning Algorithm for SMT Processors," (pdf file), Proc. of the 2008 Conf. on Parallel Architectures and Compilation Techniques (PACT'08), Oct. 2008.

[ZLKK07] Y. Zhou, V. Lakamraju, I. Koren and C.M. Krishna, "Software-Based Failure Detection and Recovery in Programmable Network Interfaces,"(pdf file), IEEE Trans. on Parallel and Distributed Systems, pp. 1539-1550, Nov. 2007.

[ABPK07] G. Agosta, L. Breveglieri, G. Pelosi and I. Koren, "Countermeasures Against Branch Target Buffer Attacks," (pdf file) , Proc. of FDTC 2007 - Fault Diagnosis and Tolerance in Cryptography, pp. 75-79, Sept. 2007.

[REGB07] F. Regazzoni, T. Eisenbarth, J. Groszschaedl, L. Breveglieri, P. Ienne, I. Koren and C. Paar, "Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits," (pdf file), Proc. of the 2007 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 508-516, Sept. 2007.

[LDCK07] J. Leung, J. Dudas, G. Chapman, I. Koren, and Z. Koren, "Quantitative Analysis of In-Field Defects in Image Sensor Arrays," (pdf file), Proc. of the 2007 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 526-534, Sept. 2007.

[HaKo07] Y. Han and I. Koren, "Simulated Annealing Based Temperature Aware Floorplanning," (pdf file) Journal of Low-Power Electronics, pp. 141-155, Vol. 3, Sept. 2007.

[BKM07] L. Breveglieri, I. Koren and P. Maistri, "An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers," (pdf file) IEEE Trans. on Computers, pp. 635-649, May 2007.

[HKK07] Y. Han, I. Koren and C. M. Krishna, "TILTS: A Fast Architectural-Level Transient Thermal Simulation Method," (pdf file) Journal of Low-Power Electronics, pp. 13-21, Vol. 3, April 2007.

[WGKK06] H. Wang, Y. Guo, I. Koren and C. M. Krishna, "Compiler-Based Adaptive Fetch Throttling for Energy Efficiency," (pdf file) Proc. of ISPASS'06 - IEEE International Symposium on Performance Analysis of Systems and Software, pp. 112-119, Mar. 2006.

[GKK05] A. Goel, I. Koren and C. M. Krishna, "Energy Aware Kernel for Hard Real-Time Systems," (pdf file) Proc. of the IEEE Conf. on Compilers, Architectures for Embedded Systems - CASES 2005, pp. 185-190, Sept. 2005.

[WoKo05] Z. Wo and I. Koren, "Synthesis of Saturating Counters Using Traditional and Non-traditional Basic Counters,"(pdf file) Proc. of the 17th IEEE Symp. on Computer Arithmetic, pp. 114-121, June 2005.

[ChKo04] G. Chapman, Y. Audet, S. Djaja, D. Cheung, I. Koren and Z. Koren, "Self-Correcting Active Pixel Sensor using Hardware and Software Correction,"(pdf file) IEEE Design & Test of Computers, pp. 544-551, Nov. 2004.

[SiKo03] M. Singh and I. Koren, ``Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters," (pdf file) IEEE Trans. on VLSI Systems, pp. 839-852, Nov. 2003.

[UnKo03] O.S. Unsal and I. Koren, "System-Level Power-Aware Design Techniques in Real-Time Systems," (Invited paper) (pdf file) Proceedings of the IEEE, pp. 1055-1069, July 2003.

[BBKMP03a] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm," (pdf file), Proc. of ASAP'03 - the Internl. Conference on Application-Specific Systems, Architectures and Processors, pp. 423-432, June 2003.

[BBKMP03b] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard," (pdf file), Proc. of the 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 105-113, Nov. 2003.

[KKO03] I. Koren, Y. Koren and B. Oomman, "Saturating Counters: Application and Design Alternatives," (pdf file), Proc. of the 16th IEEE Symp. on Computer Arithmetic, pp. 228-235, June 2003.

[BBKMP03] G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard," (pdf file), IEEE Trans. on Computers, pp. 492-505, April 2003.

Selected List of Prior Publications

Patents and patent applications:
Active pixel with built in self-repair and redundancy
Methods and Apparatus for Detecting Defects in Imaging Arrays by Image Analysis
Reducing processor energy consumption using compile-time information
Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor

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Recent Professional Activities

Associate Editor of Sustainable Computing: Informatics and Systems, 2010 - present

Associate Editor of VLSI Design Journal, 2006 - Present

Associate Editor of IEEE Computer Architecture Letters, 2006 - 2010

Associate Editor of IEEE Trans. on VLSI Systems, 2001 - 2007

IEEE Transactions on Computers, Co-Guest Editor, Special Issue on Fault Diagnosis and Tolerance in Cryptography, June 2006

Co-General Chair, FDTC 2005 - FDTC 2011 - the Annual Workshop on Fault Diagnosis and Tolerance in Cryptography

Program Committee Co-Chair, IGCC 2011 - 2nd International Green Computing Conference, August 2011

Program Committee member, the 1993 - 2011 (11th - 20th) IEEE Symposiums on Computer Arithmetic

Program Committee member, 1992- 1997 and 2000 - 2011 International Conferences on Application-Specific Systems, Architectures and Processors (ASAP)

Program Committee member, 1989- 1994 and 1996 - 2011 IEEE International Symposiums on Defect and Fault Tolerance in VLSI Systems

Program Committee member, 2008 - 2011 Euromicro Conferences on Digital System Design (EUROMICRO DSD)

Program Committee member, 2005 - 2011 International Conferences on Informatics in Control, Automation and Robotics (ICINCO)

General Chair, 17th IEEE Symposium on Computer Arithmetic, June 2005

IEEE Transactions on Computers, Co-Guest Editor, Special Issue on Computer Arithmetic , July 2000

Program Committee Co-Chair, 14th IEEE Symposium on Computer Arithmetic, 1999

Associate Editor of IEEE Trans. on Computers, 1992 - 1997

General Chair, 1996 International Conference on Parallel Architectures and Compilation Techniques (PACT'96), Boston, MA, October 21-23, 1996

General Chair, 1996 IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, November 6-8, 1996

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Simulators
Collections of online simulators created by students who have taken my classes.

· Computer Arithmetic Algorithms Simulator
· Computer Architecture Educational Tools
· Fault Tolerant Computing Simulator

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Courses

· Computer Architecture
· Hardware Organization and Design
· Fault Tolerant Computing
· Digital Computer Arithmetic
· Computer Systems Lab II
· Special Topics: Design for Manufacturability and Reliability of VLSI Circuits
· "FP'Arithmetic 97", a course on Floating-Point Arithmetic with William Kahan (UC Berkeley), at Sun, Mountain View, CA, June 1997 ( Picture 1, Picture 2).

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Department, University and Town

· Department of Electrical and Computer Engineering
· University of Massachusetts
· Directions and maps to the University

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My family

· My wife, Zahava Koren
· My older son, Yuval Koren, is the co-founder and CEO of Eye-Fi, a startup company in Mountain View, CA.
· My younger son, Yaron Koren is the founder of WikiWorks, New York, NY.

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