Zahava Koren is a senior researcher at the University of Massachusetts. She received the B.A and M.A degrees in Mathematics and Statistics from the Hebrew University in Jerusalem in 1967 and 1969, respectively, and the D.Sc. degree in Operations Research from the Technion - Israel Institute of Technology in 1976. Previously she has held positions with the Department of Statistics, University of Haifa, Departments of Industrial Engineering and Computer Science at the Technion, and the Department of Business and Economics, California State University in Los Angeles. Her main interests are Optimization in Queuing Processes, Stochastic Analysis of Computer Networks and Reliability of Computer Systems.

- I. Koren and Z. Koren, "Incorporating
Yield Enhancement into the Floorplanning Process,"
*IEEE Trans. on Computers, Special Issue on Defect Tolerance in Digital Systems,*, Vol. 49, pp. , June 2000. - I. Koren and Z. Koren,
"Defect Tolerant VLSI Circuits: Techniques and Yield
Analysis,"
*Proceedings of the IEEE*, Vol. 86, pp. 1817-1836, Sept. 1998. - Z. Koren and I. Koren, "On the Effect of
Floorplanning on the Yield of Large Area Integrated Circuits,"
*IEEE Trans. on VLSI Systems*, Vol. 5, pp. 3-14, March 1997. - R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, ``The
HYETI Defect Tolerant Microprocessor: A Practical Experiment and a
Cost-Effectiveness Analysis,"
*IEEE Trans. on Computers*, Vol. 43, Dec. 1994. - I. Koren, Z. Koren and C.H. Stapper, ``A Statistical Study of
Defect Maps of Large Area VLSI ICs,"
*IEEE Trans. on VLSI Systems*, Vol. 2, pp. 249-256, June 1994. - I. Koren, Z. Koren and C.H. Stapper, ``A Unified Negative
Binomial Distribution for Yield Analysis of Defect Tolerant Circuits,"
*IEEE Trans. on Computers*, Vol. 42, pp. 724-437, June 1993. - Z. Koren and A. Ganz, ``Efficient Performance Analysis of
Asymmetric Finite Buffer Multichannel Networks,"
*Stochastic Models*, Vol. 8, No. 3, 1992. - A. Ganz and Z. Koren, ``Performance and Design Evaluation of WDM
Stars",
*IEEE Journal on Lightwave Technology*, 1992. - I. Koren and Z. Koren, ``Discrete and Continuous Models for the
Performance of Reconfigurable Multistage Systems,"
*IEEE Trans. on Computers*, Vol. C-40, pp. 1024--1033, September 1991. - I. Koren and Z. Koren, ``On Gracefully Degrading Multi-processors
with Multi-stage Interconnection Networks,"
*IEEE Trans. on Reliability*, Special Issue on ``Reliability of Parallel and Distributed Computing Networks," April 1989. - I. Koren, Z. Koren and D.K. Pradhan, ``Designing Interconnection
Buses in VLSI and WSI for Maximum Yield and Minimum Delay,"
*IEEE Journal of Solid-state Circuits,*pp. 859-866, June 1988. - I. Chlamtac, A. Ganz and Z. Koren,
"Prioritized Demand Assignment Protocols and Their Evaluation,"
*IEEE Trans. on Communications*, Vol. 36, Feb. 1988. - Z. Koren, I. Chlamtac and A. Ganz, "A Model for Evaluating Demand Assignment Protocols with Arbitrary Workloads," Computer Communication Review, Vol. 16, No. 3, 1986.
- I. Koren, Z. Koren and S.Y.H. Su, ``Analysis of a Class of
Recovery Procedures,"
*IEEE Trans. on Computers*, Vol. C-35, pp. 703--712, August 1986.

- I. Koren, G. Chapman and Z. Koren,
``A Self-Correcting Active Pixel Camera,"
*Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 56-64, October 2000. (Complete manuscript in PostScript format). - Z. Koren, I. Koren and C.M. Krishna,
``Surge Handling as a Measure of Real-Time System Dependability,"
*Proc. of the IPPS/SPDP'98 workshop, in Parallel and Distributed Processing,*J. Rolim (Ed.), Lecture Notes in Computer Science 1388, Springer 1998, pp. 1106-1116. (Complete manuscript in PostScript format). - I. Koren and Z. Koren,
"Yield and Routing Objectives in Floorplanning,"
*Proc. of the 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 28-36, November 1998. - I. Koren and Z. Koren,
"Analysis of a Hybrid Defect-Tolerance Scheme for High-Density
Memory ICs,"
*Proc. of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 166-174, October 1997. - Z. Koren and I. Koren, ``Yield Analysis of a Novel Scheme for
Defect-Tolerant Memories,"
*Proc. of the 1996 IEEE International Conference on Innovative Systems in Silicon*, pp. 269-278, Austin, Texas, October 1996. - Z. Koren and I. Koren, ``The Impact of Floorplanning on the
Yield of Large Area ICs,"
*Proc. of Internl. Conf. on Wafer Scale Integration*, Jan. 1995. - Z. Koren and I. Koren, ``Does the Floorplan of a Chip Affect Its
Yield?"
*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 159-166, October 1993. - I. Koren, Z. Koren and C.H. Stapper, ``Analysis of Defect Maps of
Large Area VLSI ICs,"
*Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 267-276, Nov. 1992. - Z. Koren and I. Koren, ``A Model for Enhanced
Manufacturability of Defect Tolerant Integrated Circuits,"
*Proc. of the 1991 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, Pittsburgh, PA, November 1991. - A. Ganz and Z. Koren, ``WDM Passive Star - Protocols and
Performance Analysis",
*Proc. of INFOCOM'91*, Miami, FL, April 1991. - I. Koren, Z. Koren and C.H. Stapper, ``Employing the Unified
Negative Binomial Distribution for Yield Analysis of Empirical Data,"
*Proc. of the 1990 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, Grenoble, France, November 1990. - I. Koren and Z. Koren, ``Discrete and Continuous Models for the
Performance of Multi-stage Systems in the Presence of Faulty
Components,"
*Proc. of HICSS-22, Hawaii Internl. Conf. on System Sciences*, Jan. 1989. - I. Koren and Z. Koren, ``On the Bandwidth of a Multi-stage
Network in the Presence of Faulty Components,"
*Proc. of the 8th Internl. Conf. on Distributed Computing Systems*, pp. 26-32, June 1988. - I. Koren, Z. Koren and D.K. Pradhan, ``Wafer--Scale Integration of
Multi--processor Systems,"
*Proc. of HICSS-20, Hawaii Internl. Conf. on System Sciences*, pp. 13-20, Jan. 1987.

- Z. Koren and I. Koren, ``A Unified Approach for Yield Analysis
of Defect Tolerant Circuits,"
*Defect and Fault Tolerance in VLSI Systems*, Vol. 2, C.H. Stapper, V.K. Jain and G. Saucier (eds.), pp. 33-45, Plenum, 1990. - I. Koren and Z. Koren, ``Analyzing the Connectivity and Bandwidth
of Multi-processors with Multi-stage Interconnection Networks,"
*Concurrent Computations: Algorithm, Architecture and Technology,*S.K. Tewksbury, B.W. Dickinson and S.C. Schwartz (eds.), Chapter 26, Plenum, 1988.

- Z. Koren and A. Ganz, ``An Efficient Performance Model for
Asymmetric Finite Buffer Systems,"
*University of Massachusetts*, Technical Report 90-CSE-3. - D.Sc. Dissertation:``Optimal Partitioning of a Group of Servers, Where Customers Require a Variable Number of Servers", Technion, 1976.

Links:

Northampton-Amherst Chapter of Hadassah

My older son, Yuval Koren,
is the CEO of Eye-Fi, a startup company in Menlo Park, CA.

My younger son,
Yaron Koren is self-employed,
New York, NY.

Last update: March 15, 2001