Yield and Reliability of VLSI
Circuits

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Formely supported by NSF, CISE: Design Automation Program, and by CISM (Center for Integrated Space Microsystems) at JPL,

Israel Koren, Professor

People that were involved in this project

Tutorial: "Yield: Statistical Modeling and Enhancment Techniques," (PS format) (or PDF format) presented at the Yield Optimization and Test (YOT'01) Workshop, Nov. 2001.

Presentation at JPL, System-on-a-Chip Meeting, April 20-21, 1998.

Research has focused on the following directions:

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List of Yield and Reliability Related Publications ( copyright note )

Journal Papers

  1. * M. Singh and I. Koren, ``Fault Sensitivity Analysis and Reliability Enhancement of Analog-to-Digital Converters," IEEE Trans. on VLSI Systems, pp. 839-852, Nov. 2003. (Complete manuscript in PDF format).
  2. * I. Koren and Z. Koren, "Incorporating Yield Enhancement into the Floorplanning Process," IEEE Trans. on Computers, Special Issue on Defect Tolerance in Digital Systems,, Vol. 49, pp. , June 2000. (Complete manuscript in pdf format).
  3. * I. Koren and Z. Koren, "Defect Tolerant VLSI Circuits: Techniques and Yield Analysis," Proceedings of the IEEE, Vol. 86, pp. 1817-1836, Sept. 1998. (Complete manuscript in pdf format).
  4. * Z. Chen and I. Koren, "Three Layer Routing for Reliability Enhancement," Journal of Microelectronic Systems Integration, Vol 5, No 4, pp. 209-219, Dec. 1997. (Complete manuscript in PDF format).
  5. * Z. Koren and I. Koren, "On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits," IEEE Trans. on VLSI Systems, Vol. 5, pp. 3-14, March 1997. (Complete manuscript in pdf format).
  6. * I. A. Wagner and I. Koren, "An Interactive VLSI CAD Tool for Yield Estimation," IEEE Trans. on Semiconductor Manufacturing, Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 130-138, May 1995. (Complete manuscript in pdf format).
  7. * V.K.R. Chiluvuri and I. Koren, "Layout Synthesis Techniques for Yield Enhancement," IEEE Trans. on Semiconductor Manufacturing, Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 178-187, May 1995. (Won the 1995 Best Paper Award of the IEEE Trans. on Semiconductor Manufacturing, (Complete text in PDF format).
  8. * R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, "The HYETI Defect Tolerant Microprocessor: A Practical Experiment and a Cost-Effectiveness Analysis," IEEE Trans. on Computers, Vol. 43, pp. 1398-1406, Dec. 1994. (Complete manuscript in PDF format).
  9. * I. Koren, Z. Koren and C.H. Stapper, "A Statistical Study of Defect Maps of Large Area VLSI ICs," IEEE Trans. on VLSI Systems, Vol. 2, pp. 249-256, June 1994. (Complete manuscript in PDF format).
  10. * I. Koren, Z. Koren and C.H. Stapper, "A Unified Negative Binomial Distribution for Yield Analysis of Defect Tolerant Circuits," IEEE Trans. on Computers, Vol. 42, pp. 724-437, June 1993. (Complete manuscript in PDF format).
  11. * I. Koren and A.D. Singh, "Fault Tolerance in VLSI Circuits," Computer, Special Issue on Fault-Tolerant Systems, Vol. 23, pp. 73-83, July 1990. (Complete manuscript in PDF format).
  12. * Z. Koren and I. Koren, "A Unified Approach for Yield Analysis of Defect Tolerant Circuits," Defect and Fault Tolerance in VLSI Systems, Vol. 2, C.H. Stapper, V.K. Jain and G. Saucier (eds.), pp. 33-45, Plenum, 1990.
  13. I. Koren and C.H. Stapper (Guest Editors), "Introduction - Special Section on High-Yield VLSI Systems," IEEE Trans. on Computers, Vol. 38, pp. 481-482, April 1989.
  14. I. Koren (ed.), Defect and Fault Tolerance in VLSI Systems, Vol. 1, Plenum, 1989.
  15. * I. Koren and C.H. Stapper, "Yield Models for Defect Tolerant VLSI Circuits: A Review," Defect and Fault Tolerance in VLSI Systems, Vol. 1, I. Koren (ed.), pp. 1-21, Plenum, 1989. (Reprints of this and five other papers in this list appear in Manufacturing Yield Evaluation of VLSI/WSI Systems, B. Ciciani (editor), IEEE Computer Society Press, Los Alamitos, 1995,) (Complete manuscript in PDF format).
  16. * I. Koren, "The Effect of Scaling on the Yield of VLSI Circuits," Yield Modelling and Defect Tolerance in VLSI, W.R. Moore, W. Maly and A. Strojwas (Eds.), pp. 91-99, Adam Hillger Ltd., 1988. (Complete manuscript in PDF format).
  17. * I. Koren, Z. Koren and D.K. Pradhan, "Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay," IEEE Journal of Solid-state Circuits, Vol. 23, pp. 859-866, June 1988.
  18. * I. Koren and D. Pradhan, "Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems," IEEE Trans. on Comp., Vol. C-36, pp. 344-355, Mar. 1987.
  19. * I. Koren and D.K. Pradhan, "Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-processor Systems," Proc. of IEEE, Special Issue on Fault-Tolerance in VLSI, Vol. 74, No. 5, pp. 699-711, May 1986.
  20. * I. Koren and M.A. Breuer, "On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays," IEEE Trans. on Comp., Vol. C-33, pp. 21-27, Jan. 1984.
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Refereed Conference Papers

  1. * A. Maheshwari, I. Koren and W. Burleson, ``Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits," Proc. of the 2004 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 377-385, October 2004 (Complete manuscript in PDF format).
  2. * A. Maheshwari, I. Koren and W. Burleson, ``Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits," Proc. of the 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 597-604, November 2003 (Complete manuscript in PDF format).
  3. * M. Singh and I. Koren, ``Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)," Proc. of the International Symposium on Quality of Electronic Design (ISQED'02), pp. 286-291, March 2002. (Complete manuscript in PDF format).
  4. * M. Singh and I. Koren, ``Reliability Enhancement Techniques for Analog-to-Digital Converters (ADCs)," Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 347-353, October 2001. (Complete manuscript in PDF format).
  5. * I. Koren, G. Chapman and Z. Koren, ``Advanced Fault-Tolerance Techniques for a Color Digital Camera-On-A-Chip," Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 3-10, October 2001. (Complete manuscript in PDF format).
  6. * M. Singh, R. Rachala and I. Koren, ``Transient Fault Sensitivity Analysis of Analog-to-Digital Converters," Proc. of WVLSI 2001, April 2001. (Complete manuscript in PDF format).
  7. * R. K. Prasad and I. Koren, ``Constructive Floorplanning with a Yield Objective," Proc. of the International Symposium on Quality of Electronic Design, pp. 261-266, March 2001. (Complete manuscript in PDF format).
  8. * R. K. Prasad and I. Koren, ``The Effect of Placement on Yield for Standard Cell Designs," Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 3-11, October 2000. (Complete manuscript in PDF format).
  9. * I. Koren, G. Chapman and Z. Koren, ``A Self-Correcting Active Pixel Camera," Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 56-64, October 2000. (Complete manuscript in PDF format).
  10. * I. Koren, ``Should Yield be a Design Objective?" (invited paper), Proc. of the International Symposium on Quality of Electronic Design, pp. 115-120, March 2000. (Complete manuscript in PDF format).
  11. * A. Venkataraman and I. Koren, "Determination of yield bounds prior to routing," Proc. of the 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 4-13, November 1999. (Complete manuscript in PDF format).
  12. * I. Koren and Z. Koren, "Yield and Routing Objectives in Floorplanning," Proc. of the 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 28-36, November 1998. (Complete manuscript in PDF format).
  13. * I. Koren and Z. Koren, "Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs," Proc. of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 166-174, October 1997. (Complete manuscript in PDF format).
  14. * Z. Chen and I. Koren, "Crosstalk Minimization in Three-Layer HVH Channel Routing," Proc. of the 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 38-42, October 1997. (Complete manuscript in PDF format).
  15. * A. Venkataraman, H. Chen and I. Koren, "Yield Enhanced Routing for High-Performance VLSI Designs," Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97, pp. 50-60, October 1997.
  16. * Z. Chen and I. Koren, "Technology Mapping for Hot-Carrier Reliability Enhancement," Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97, pp. 42-50, October 1997. (Complete manuscript in PDF format).
  17. * Z. Chen and I. Koren, "Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing," Proc. of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 76-84, November 1996. (Complete manuscript in PDF format).
  18. * A. Venkataraman and I. Koren, "Trade-offs between Yield and Reliability Enhancement," Proc. of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 67-75, November 1996. (Complete manuscript in PDF format).
  19. * V.K.R. Chiluvuri and I. Koren, "Wire Length and Via Reduction for Yield Enhancement," Proc. of the 1996 SPIE Microelectronics Manufacturing Conference, pp. 103-111, Austin, Texas, Oct. 1996.
  20. * I. Koren and Z. Koren, "Yield Analysis of a Novel Scheme for Defect-Tolerant Memories," Proc. of the 1996 IEEE International Conference on Innovative Systems in Silicon, pp. 269-278, Austin, Texas, October 1996.
  21. * I. Koren, "Catastrophic Yield, Parametric Yield and Reliability: Can We Still View Them as Disjoint Issues?," invited paper, Proc. of the 5th ACM/SIGDA Physical Design Workshop, pp. 207-209, April 1996.
  22. B. Iyer, R. Karri and I. Koren, "Phantom Redundancy: A High-Level Synthesis Technique for Manufacturability," Proc. of ICCAD-95, The Internl. Conference on CAD, pp. 658-661, Nov. 1995.
  23. * I. A. Wagner and I. Koren, "The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines," Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 46-54, November 1995. (Complete manuscript in PDF format).
  24. * Z. Chen and I. Koren, "Layer Assignment for Yield Enhancement," Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 173-180, November 1995. (Complete manuscript in PDF format).
  25. * V.K.R. Chiluvuri and I. Koren, "Yield Enhancement vs. Performance Improvement in VLSI Circuits," Proc. of ISSM-95, The Intern. Sympos. on Semiconductor Manufacturing , pp. 28-31, Austin, Sept. 1995.
  26. * Z. Chen and I. Koren, "Techniques for Yield Enhancement of VLSI Adders," Proc. of ASAP 95 - the Internl. Conference on Application-Specific Array Processors, pp. 222-229, July 1995. (Complete manuscript in PDF format).
  27. * Z. Koren and I. Koren, "The Impact of Floorplanning on the Yield of Fault-Tolerant ICs," Proc. of Internl. Conf. on Wafer Scale Integration, pp. 329-338, Jan. 1995.
  28. * Z. Chen and I. Koren, "A Yield Study of VLSI Adders," Proc. of the 1994 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 239-245, Oct. 1994. (Complete manuscript in PDF format).
  29. * V.K.R. Chiluvuri, I. Koren and J. L. Burns, "The Effect of Wire Length Minimization on Yield," Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 97-105, October 1994.
  30. * I. A. Wagner and I. Koren, "An Interactive Yield Estimator as a VLSI CAD tool," Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 167-174, October 1993.
  31. * V.K.R. Chiluvuri and I. Koren, "Topological Optimization of PLAs for Yield Enhancement," Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 175-182, October 1993.
  32. * Z. Koren and I. Koren, "Does the Floorplan of a Chip Affect Its Yield?" Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 159-166, October 1993.
  33. * V.K.R. Chiluvuri and I. Koren, "New Routing and Compaction Strategies for Yield Enhancement," Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 325-334, November 1992.
  34. * W. Che and I. Koren, "Fault Spectrum Analysis for Fast Spare Allocation in Reconfigurable Arrays," Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 60-69, November 1992.
  35. * I. Koren, Z. Koren and C.H. Stapper, "Analysis of Defect Maps of Large Area VLSI ICs," Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 267-276, Nov. 1992.
  36. Z. Koren and I. Koren, "A Model for Enhanced Manufacturability of Defect Tolerant Integrated Circuits," Proc. of the 1991 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 81-92, November 1991.
  37. * I. Koren, "Projecting the Yield of Defect Tolerant ICs," invited paper, Proc. of the IEICE Fault Tolerant Systems Workshop in Japan, Vol. 91, No. 122, FTCS 91-25, pp. 47-54, July 1991.
  38. * I. Koren, Z. Koren and C.H. Stapper, "Employing the Unified Negative Binomial Distribution for Yield Analysis of Empirical Data," Proc. of the 1990 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, Grenoble, Nov. 1990.
  39. * J-J. Shen and I. Koren, "Yield Enhancement Designs for WSI Cube Connected Cycles," Proc. of Internl. Conf. on Wafer Scale Integration, pp. 289-298, Jan. 1989.
  40. * I. Koren and D.K. Pradhan, "Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement," Proc. of the 15th Internl. Symp. on Fault-Tolerant Computing, pp. 330-335, June 1985.
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koren 'at' euler.ecs.umass.edu
Last update: December 30, 2002