Selected Research Papers:

• M. Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, and E. Boutillon, Data-Flow Transformations using Taylor Expansion Diagrams Design, Automation and Test in Europe Conference, DATE'07, April, 2007.

• M. Ciesielski, P. Kalla, S. Askar, Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs, IEEE Transactions on Computers, Vol. 55, No. 9, pp. 1188-1201, Sept. 2006.

• J. Guillot, E. Boutillon, D. Gomez-Prado, S. Askar, Q. Ren, and M. Ciesielski, Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams, Design, Automation and Test Conference in Europe, DATE'06, March 2006.

• Z. Zeng, K.R. Talupuru, and M. Ciesielski, Functional Test Generation based on Word-level SAT, in Journal of Systems Architecture. Vol.51, Issue 8, August 2005, pp. 488-511. Elsevier Publishers, 2005.

• D. Gomez-Prado, Q. Ren, S. Askar, M. Ciesielski, E. Boutillon, Variable Ordering for Taylor Expansions Diagrams, IEEE Intl. High Level Design Validation and Test Workshop>, HLDVT-04, pp. 55-59, Nov. 2004.

• Z. Zeng, Q. Zhang, I. Harris, M. Ciesielski, Fast Compputation of Data Correlation using BDDs , Design Automation & Test in Europe, DATE-2003, pp. 122-127, March 2003.

• D. Pradhan, S. Askar, M. Ciesielski, Mathematical Framework for Representing Discrete Functions as Word-level Polynomials, IEEE Intl. High Level Design Validation and Test Workshop, HLDVT-03, pp. 135-139, Nov. 2003.

• C. Yang, M. Ciesielski, BDS: BDD-based Logic Optimization System , IEEE Transactions on CAD, Vol. 21, pp. 866-876, July 2002.

• M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification , Design Automation & Test in Europe, DATE-2002, p. 285-289, March 2002.

• M. Ciesielski, S. Askar, S. Levitin, Analytical Approach to Layout Generation of Datapath Cells , IEEE Transactions on CAD, Vol. 21, No. 12, pp. 1480-1488, Dec. 2002

• P. Kalla, M. Ciesielski, A Comprehensive Approach to Partial Scan Problem using Implicit State Enumeration , IEEE Trans. on Computer-Aided Design, Vol. 21, pp. 810-826, July 2002.

• Z. Zeng, P. Kalla, M. Ciesielski, LPSAT: A Unified Approach to RTL Satisfiability (PS file). Design, Automation and Test in Europe Conference, DATE-2001, pp. 398-402, March 2001.

• M. Fujita, Y. Matsunaga, M. Ciesielski, ``Multi-Level Logic Optimization'', in Logic Synthesis and Verification, Kluwer Academic Publishers, ed. by T. Sasao and S. Hassoun. Chapter 2, pp. 29-67, Aug. 2001.

• Z. Zeng, M. Ciesielski, B. Rouzeyre, Functional Test Generation using Constraint Logic Programming , in Proc. IFIP VLSI-SOC Conference Dec. 2001.

• S. Askar, M. Ciesielski, Transistor Placement for Custom Datapath Cells (PS file). 15th Design of Circuits and Integrated Systems Conference, DCIS-2000.

• P. Kalla, M. Ciesielski, A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm. (PS file). Design, Automation and Test in Europe Conference, DATE-2000.

• C. Yang, V. Singhal, M. Ciesielski, BDD Decomposition for Efficient Logic Synthesis (PS file). Intl. Conference on Computer Design: VLSI in Computers and Processors, ICCD'99 .

• S. Askar, M. Ciesielski, Analytical Approach to Custom Datapath Design (PDF file). Intl. Conference on Computer-Aided Design, ICCAD'99.

• P. Kalla, M. Ciesielski, Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence , Design & Test in Europe Conference, DATE'99.

• B. Iyer, M. Ciesielski, Reencoding for Cycle-Time Minimization under Fixed Encoding Length , (PDF file). Intl. Conference on Computer-Aided Design, ICCAD'98.

• P. Kalla, M. Ciesielski, A Comprehensive Approach to Partial Scan Problem using Implicit State Enumeration , International Test Conference, 1998.

• S. Bommu, M. Ciesielski, P. Kalla, N. O'Neill, Sequential Logic Optimization with Implicit Retiming and Resynthesis, Proceedings of International Conference on VLSI'97.

• B. Iyer, M. Ciesielski, METAMORPHOSIS: State Assignment by Retiming and Re-encoding, Intl. Conference on Computer-Aided Design, ICCAD'96, 1996.

• P. Kalla, M. Ciesielski, Testability of Sequential Circuits with Multi-Cycle False Paths, 15th IEEE VLSI Test Symposium, 1997.

• W. Burleson, M. Ciesielski, F. Klass, W. Liu, Wave-pipelining: A tutorial and Survey of Recent Research (ps.gz file). IEEE Transactions on VLSI, Vol.6, No.3, pp. 464-474, Sept. 1998.

• Z. Hasan, M. Ciesielski, FSM Decomposition and Functional Verification of FSM Networks, VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, 1995.

• S. Yang, M. Ciesielski, Optimum and Suboptimum Algorithms for Input Encoding and its Relationship to Logic Minimization , IEEE Trans. on CAD, Jan. 1991.