PUBLICATIONS
Journal Papers and Book Chapters
- R.
Tessier, V. Betz, D. Neto, A. Egier, and T. Gopalsamy, Power Efficient RAM Mapping Algorithms for FPGA
Embedded Memory Blocks, in IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 26, no. 2, Feb. 2007,
pp. 278-290. postscript, pdf
- P.
Menon, W. Xu, and R. Tessier,
Design-Specific Path Delay Testing in Lookup Table-based FPGAs, in IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 25, no. 5,
May 2006, pp. 867-877. postscript, pdf
- R.
Tessier, D. Jasinski, A. Maheshwari, A. Natarajan, W. Xu, and W. Burleson, An Energy-Aware Active Smart Card, in IEEE Transactions on VLSI Systems, vol.
13, no. 10, Oct. 2005, pp. 1190-1199. postscript, pdf
- R.
Tessier, S. Swaminathan, R. Ramaswamy, D. Goeckel, and W. Burleson, A Reconfigurable, Power-Efficient Adaptive
Viterbi Decoder, in
IEEE Transactions on VLSI Systems, vol. 13, no. 4, April
2005, pp. 484-488. postscript,
pdf
- J.
Liang, A. Laffely, S. Srinivasan, and R. Tessier, An Architecture and Compiler for Scalable
On-Chip Communication, in IEEE Transactions on VLSI Systems, vol. 12, no. 7,
July 2004, pp. 711-726. postscript,
pdf
- G.
Farquharson, W. Junek, A. Ramanathan, S. Frasier, R. Tessier, D.
McLaughlin, M. Sletten, and J. Toporkov, A Pod-Based Dual-Beam InSAR, in IEEE Transactions on Geoscience and Remote
Sensing Letters, vol 1, no. 2, April 2004, pp. 62-65. postscript, pdf
- A.
Maheshwari, W. Burleson, and R. Tessier, Trading Off Transient Fault-tolerance and Power Consumption in
Deep Submicron VLSI Circuits, in IEEE Transactions on VLSI Systems, vol 12, no. 3,
March 2004, pp. 299-311. postscript,
pdf
- P.
Jain, A. Laffely, W. Burleson, R. Tessier, and D. Goeckel, Dynamically Parameterized Algorithms and
Architectures to Exploit Signal Variations, in Journal of VLSI Signal Processing,
vol 36, no. 1, January 2004, pp. 27-40. postscript, pdf
- S.
Krishnamoorthy and R. Tessier, Technology
Mapping Algorithms for Hybrid FPGAs Containing Lookup-Tables and PLAs, in IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol 22, no. 5, May 2003,
pp. 545-559. postscript,
pdf
- I. G.
Harris and R. Tessier, Testing and
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures, in IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol 21, no. 11, November
2002, pp. 1337-1343. postscript,
pdf
- M.
Kudlugi and R. Tessier, Static
Scheduling of Multi-domain Circuits for Fast Functional Verification, in IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol 21, no. 11, November
2002, pp. 1253-1268. postscript,
pdf
- R.
Tessier and S. Jana, Incremental
Compilation for Parallel Logic Verification Systems, in IEEE Transactions on VLSI Systems ,
vol 10, no. 5, October 2002, pp 623-636. postscript, pdf
- N.
Vemuri, P. Kalla, and R. Tessier, BDD-Based
Logic Synthesis for LUT-Based FPGAs, in ACM Transactions on Design Automation of
Electronic Systems , vol. 7, no. 4, October 2002, pp
501-525. postscript, pdf
- R.
Tessier, Fast Placement Approaches
for FPGAs, in ACM
Transactions on Design Automation of Electronic Systems , vol. 7, no. 2,
April 2002, pp 284-305. postscript,
pdf
- R.
Tessier and W. Burleson, Reconfigurable
Computing and Digital Signal Processing: Past, Present, and Future, in Programmable Digital Signal Processors ,
Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002
- R.
Tessier and W. Burleson, Reconfigurable Computing and Digital Signal
Processing: A Survey,
in Journal of VLSI Signal Processing , May/June 2001, pp.
7-27, postscript, pdf
- J.
Babb, R. Tessier, M. Dahl, S. Hanano, D. Hoki, and A. Agarwal, Logic Emulation with Virtual Wires, in IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, June 1997. postscript,
pdf
Refereed Conference and Workshop Papers
- K.
Tinmaung, D. Howland, and R. Tessier, Power-aware FPGA Logic Synthesis Using
Binary Decision Diagrams, in the
Proceedings of the ACM/SIGDA International Symposium on Field Programmable
Gate Arrays, Monterey, CA, February 2007. pdf
- R.
Tessier, V. Betz, D. Neto, and T. Gopalsamy, Power-aware RAM Mapping
for FPGA Embedded Memory Blocks, in
the Proceedings of the ACM/SIGDA International Symposium on Field
Programmable Gate Arrays, Monterey, CA, February 2006. pdf
- L.
Atieno, J. Allen, D. Goeckel, and R. Tessier, An Adaptive Reed-Solomon
Errors-and-Erasures Decoder, in
the Proceedings of the ACM/SIGDA International Symposium on Field
Programmable Gate Arrays, Monterey, CA, February 2006. pdf
- R.
Khasgiwale, L. Krnan, A. Perinkulam, and R. Tessier, Reconfigurable
Data Acquisition System for Weather Radar Applications, in the Proceedings of the IEEE Midwest Symposium
on Circuits and Systems, Cincinnati, Ohio, August 2005. pdf
- D.
Perkovic, S. Frasier, R. Tessier, M. Sletten, and J. Toporkov, An Airborne, Pod-mounted Dual Beam
Interferometer, in the
Proceedings of IEEE Aerospace Conference, Big Sky, Montana, March
2005. pdf
- J.
Liang, R. Tessier, and D. Goeckel, A Dynamically-Reconfigurable,
Power-Efficient Turbo Decoder, in
the Proceedings of the IEEE Symposium on Field-Programmable Custom
Computing Machines, Napa, California, April 2004. pdf
- A.
Laffely, J. Liang, R. Tessier, and W. Burleson, Adaptive System on a
Chip: A Backbone for Power-Aware Signal Processing Cores, Proceedings
of the IEEE Conference on Image Processing, Barcelona, Spain, September
2003. pdf
- W.
Xu, R. Ramanarayanan, and R. Tessier, Adaptive
Fault Tolerance for Networked Reconfigurable Systems, in the Proceedings of the IEEE Symposium on
Field-Programmable Custom Computing Machines, Napa, California,
April 2003. pdf
- J.
Liang, R. Tessier, and O. Mencer, Floating Point Unit Generation and
Evaluation for FPGAs, in the
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing
Machines, Napa, California, April 2003. pdf
- A.
Natarajan, D. Jasinski, W. Burleson, and R. Tessier, A Hybrid Adiabatic
Content Addressable Memory for Ultra-Low Power Applications, in the Proceedings
of the IEEE/ACM Great Lakes Symposium on VLSI, Washington, D.C.,
April 2003. pdf
- R.
Ramaswamy and R. Tessier, The
Integration of SystemC and Hardware-assisted Verification, in the Proceedings of the 12th International
Conference on Field-Programmable Logic and Applications, Montpelier, France.
September 2002. pdf
- A.
Maheshwari, W. Burleson and R. Tessier, Trading Off Reliability and Power Consumption in Ultra-Low Power
Systems, in the
Proceedings of the International Symposium on Quality Electronic Design,
San Jose, California, March 2002. pdf
- S.
Swaminathan, R. Tessier, D. Goeckel, and W. Burleson, A Dynamically Reconfigurable Adaptive Viterbi
Decoder, in the
Proceedings of the 10th International ACM/SIGDA Symposium on Field
Programmable Gate Arrays, Monterey, California, February
2002. pdf
- A. Laffely,
J. Liang, P. Jain, N. Weng, W. Burleson and R. Tessier, Adaptive Systems on a Chip (aSoC) for Low-Power
Signal Processing,
in the Proceedings of the Asilomar Conference on Signals, Systems, and
Computers, Monterey, California, November 2001. pdf
- M.
Kudlugi, C. Selvidge, and R. Tessier, Static Scheduling of Multi-Domain Memories for Functional
Verification, in the
Proceedings of the International Conference on Computer Aided Design,
San Jose, California,
November 2001. pdf
- I. G.
Harris, P. Menon, and R. Tessier, BIST-Based
Delay Path Testing in FPGA Architectures, in the Proceedings of the International Test
Conference , Baltimore, Maryland, October 2001. pdf
- M.
Kudlugi, C. Selvidge, and R. Tessier, Static Scheduling of Multiple Asynchronous Domains for Functional
Verification, in the
Proceedings of the 38th Design Automation Conference, Las
Vegas, Nevada, June 2001. pdf
- M.
Kudlugi and R. Tessier, Multi-domain
Communication for FPGA-based Logic Emulation, in the Proceedings of the 10th International
Workshop on Logic and Synthesis, Lake
Tahoe, Nevada,
June 2001. pdf
- M.
Singh, S. Thampuran, P. Jain, R. Tessier, C. A. Moritz, Short Range Wireless Connectivity for Next
Generation Architectures, in the Proceedings of the 2001 International Conference on
Parallel and Distributed Processing Techniques and Applications
(PDPTA'2001) , Las Vegas, Nevada, June 2001. pdf
- W.
Burleson, R. Tessier, D. Goeckel, S. Swaminathan, P. Jain, J. Euh, S.
Venkatraman and V. Thyagarajan, Dynamically
Parameterized Algorithms and Architectures to Exploit Signal Variations
for Improved Performance and Reduced Power, in the Proceedings of the International
Conference on Acoustics, Speech, and Signal Processing, 2001 (ICASSP'01). Salt
Lake City, Utah, May
2001, pdf
- I. G.
Harris and R. Tessier, Diagnosis
of Interconnect Faults in Cluster-Based FPGA Architectures, in the Proceedings of the International
Conference on Computer Aided Design , San Jose, California,
November 2000. postscript, pdf
- J.
Liang, S. Swaminathan, and R. Tessier, aSOC: A Scalable, Single-Chip Communications Architecture, in the Proceedings of the IEEE International
Conference on Parallel Architectures and Compilation Techniques,
Philadelphia, PA.
October 2000. postscript, pdf
- R.
Tessier and H. Giza, Balancing
Logic Utilization and Area Efficiency in FPGAs, in the Proceedings of the 10th International
Conference on Field-Programmable Logic and Applications, Villach, Austria.
August 2000. postscript,
pdf
- S.
Krishnamoorthy, S. Swaminathan, and R. Tessier, Area-Optimized Technology Mapping for Hybrid
FPGAs, in the
Proceedings of the 10th International Conference on Field-Programmable
Logic and Applications, Villach, Austria. August 2000. postscript, pdf
- I. G.
Harris and R. Tessier, Interconnect
Testing in Cluster-Based FPGA Architectures, in the Proceedings of the 37th Design
Automation Conference, Los
Angeles, California,
June 2000. postscript, pdf
- V.
Lakamraju and R. Tessier, Tolerating
Operational Faults in Cluster-based FPGAs, in the Proceedings of the 8th International
ACM/SIGDA Symposium on Field Programmable Gate Arrays,
Monterey, California, February 2000. postscript, pdf
- R.
Tessier, Frontier: A Fast
Placement System for FPGAs, in the Proceedings of the Tenth IFIP International Conference on
VLSI, Lisbon, Portugal, December 1999, postscript, pdf,
- R.
Tessier, Incremental Compilation
for Logic Emulation, in
the Proceeding of the 10th IEEE International Workshop on Rapid Systems
Prototyping, Clearwater, Florida, June 1999, postscript, pdf,
- R.
Tessier, Negotiated A* Routing for
FPGAs, in the
Proceeding of the 5th Canadian Workshop on Field Programmable Devices,
Montreal, Quebec, Canada, June 1998, postscript, pdf,
- M.
Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki, and A. Agarwal, Emulation of a Sparc Microprocessor with the MIT
Virtual Wires Emulation System, in the Proceedings of the IEEE Workshop on
FPGAs for Custom Computing Machines, Napa, California, April
1994. postscript
- R.
Tessier, J. Babb, M. Dahl, S. Hanano, and A. Agarwal, The Virtual Wires Emulation System: A
Gate-Efficient ASIC Prototyping Environment, in the Proceedings of the 2nd International
ACM/SIGDA Workshop on Field Programmable Gate Arrays,
Berkeley, California, February 1994. postscript,
pdf
- J.
Babb, R. Tessier, and A. Agarwal, Virtual
Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, in the Proceedings of the IEEE Workshop on
FPGAs for Custom Computing Machines, Napa, California,
April 1993. postscript
Theses
- Kevin
Oo Tinmaung, Power-Aware FPGA
Logic Synthesis Using Binary Decision Diagrams, Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
May 2006.
- Murali
Kudlugi, Static Scheduling of
Multi Domain Circuits for Functional Verification, Ph.D. thesis, Department of Electrical and Computer
Engineering, University of Massachusetts, Amherst, May 2005.
- Rishi
Khasgiwale, Reconfigurable Data
Acquisition System for Weather Radar Applications , Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
February 2005. pdf
- Lilian
Atieno, Run-Time Dynamically
Reconfigurable Reed-Solomon Decoder System , Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
February 2005.
- Eric
Keller, Programming Model for
Network Processing on FPGAs , Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
February 2005. pdf
- Jian
Liang, Development and
Verification of System-on-a-Chip Communication Architecture,
Ph.D. thesis, Department of
Electrical and Computer Engineering, University of
Massachusetts, Amherst, May 2004. pdf
- Srini
Krishnamoorthy, Design Mapping
Algorithms for Hybrid FPGAs, Ph.D. thesis, Department of Electrical and Computer Engineering,
University of Massachusetts, Amherst, February 2004.
- David
Jasinski, An Energy-Aware Active
Smart-Card Architecture, Master's thesis, Department of Electrical and Computer Engineering,
University of Massachusetts, Amherst, September 2003.
- Ramshankar
Ramanarayanan, Self-Test and
Reconfiguration to Support Fault Tolerance in VLIW Processors,
Master's thesis, Department of
Electrical and Computer Engineering, University of
Massachusetts, Amherst, September 2003.
- Arun
Ramanathan, Acquisition of Sensing
Data on a Reconfigurable Platform, Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
February 2003.
- Vibhor
Garg, A PCI-X Bus Transactor Model
for SOC Verification Using Co-Modeling, Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
February 2002.
- Sriram
Swaminathan, An FPGA Based
Adaptive Viterbi Decoder, Master's thesis, Department of Electrical and Computer Engineering,
University of Massachusetts, Amherst, September 2001.
- Ramaswamy
Ramasway, Integration of SystemC
with an Ikos VirtuaLogic Emulator, Master's thesis, Department of Electrical and
Computer Engineering, University of Massachusetts, Amherst,
September 2001, pdf
- Navin
Vemuri, BDD-based Logic Synthesis
for LUT-Based FPGAs, Master's
thesis, Department of Electrical and Computer Engineering,
University of Massachusetts, Amherst, May 2001,
- Russell
Tessier, Fast Place and Route
Approaches for FPGAs, Ph.D.
thesis, Department of Electrical Engineering and Computer Science,
MIT, February 1999, postscript, pdf
Unrefereed Publications
- F. Junyent, V. Chandrasekar, D.J.
McLaughlin1, S. Frasier, E. Insanic, R. Ahmed, N. Bharadwaj, E. Knapp, L.
Krnan, and R. Tessier, Salient Features of Radar Nodes
of the First Generation NetRad System, in the Proceeding of the International
Geoscience and Remote Sensing Symposium, Seoul, Korea, July
2005, pdf
(extended abstract)
- W.
Junek, A. Ramanathan, G. Faquharson, S. Frasier, R. Tessier, D.
McLaughlin, M. Sletten, and J. Toporkov, First Observations with the UMass Dual-Beam InSAR, in the Proceeding of the International
Geoscience and Remote Sensing Symposium, Toulouse, France,
July 2003, pdf (extended
abstract)
- A.
Ramanathan, R. Tessier, D. McLaughlin, J. Carswell, and S. Frasier, Acquisition of Sensing Data on a Reconfigurable
Platform, in the
Proceeding of the International Geoscience and Remote Sensing Symposium,
Sydney, Australia, July 2001, pdf
(extended abstract)
- R.
Tessier, Programmable Cellular
Logic: Past, Present, and Future, Department of Electrical Engineering and
Computer Science, Massachusetts Institute of Technology, Area Exam Report,
February 1994. postscript,
pdf