• M. El Bouazzati, P. Tanguay, G. Gogniat, and R. Tessier, Diwall: A Lightweight Host Intrusion Detection System against Jamming and Packet Injection Attacks, in ACM Transactions on Embedded Computing Systems, accepted/to appear. 
  
• N. Albartus, M. Ender, J.-N. Moller, M. Fyrbiak, C. Paar, and R. Tessier, On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP), in ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 2, pp. 1-28, April 2024. 
  
• M. Stojilovic, K. Rasmussen, F. Regazzoni, M. Tahoori, and R. Tessier, A Visionary Look at the Security of Reconfigurable Cloud Computing, in Proceedings of the IEEE, vol. 111, no. 12, pp. 1548-1571, December 2023. 
  
• S. Moini, A. Deric, X. Liang, G. Provelengios, W. Burleson, R. Tessier, and D. Holcomb, Voltage Sensor Implementations for Remote Power Attacks on FPGAs, in ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 1, pp. 11.1-11.21, March 2023. 
  
• X. Li, P. Stanwicks, G. Provelengios, R. Tessier, and D. Holcomb, Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud, in ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 1, pp. 3.1-3.20, March 2023. 
  
• C. Bobda, J. M. Mbongue, P. Chow, M. Ewais, N. Tarafdar, J. C. Vega, K. Eguro, D, Koch, S. Handagala, M. Leeser, M. Herbordt, H. Shahzad, P. Hofste, B. Ringlein, J. Szefer, A. Sanaullah, and R. Tessier, The Future of FPGA Acceleration in Datacenters and the Cloud, in ACM Transactions on Reconfigurable Technology and Systems, vol. 15, no. 3, September 2022, pp. 1-42. 
  
• F. Stoltz, N. Albartus, J. Speith, S. Klix, C. Nasenberg, A. Gula, M. Fyrbiak, C. Paar, T. Guneysu, and R. Tessier, LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security, in IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2021, no. 34, September 2021, pp. 412-446. 
  
• G. Provelengios, D. Holcomb, and R. Tessier, Mitigating Voltage Attacks in Multi-Tenant FPGAs, in ACM Transactions on Reconfigurable Technology and Systems, vol. 14, no. 2, August 2021, pp. 1-24. 
  
• S. Moini, S. Tian, D. Holcomb, J. Szefer, and R. Tessier, Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs, in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 2, June 2021, pp. 357-370. 
  
• G. Provelengios, D. Holcomb, and R. Tessier, Power Distribution Attacks in Multitenant FPGAs, in IEEE Transactions on VLSI Systems, vol. 28, no. 12, December 2020, pp. 2685-2698. 
  
• X. Zhang, X. Shao, G. Provelengios, N. K. Dumpala, L. Gao, and R. Tessier, CoNFV: A Heterogeneous Platform for Scalable Network Function Virtualization, in ACM Transactions on Reconfigurable Technology and Systems, vol. 14, no. 1, November 2020, pp. 1-29. 
  
• M. Fyrbiak, S. Wallat, P. Swierczynski, M. Hoffman, S. Hoppach, M. Wilhelm, T. Weidlich, R. Tessier and C. Paar, HAL - The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion, in IEEE Transactions on Dependable and Secure Computers, vol. 16, no. 3, May/June 2019, pp. 498-510. 
  
• M. Usmani, S. Keshavarz, E. Matthews, L. Shannon, R. Tessier and D. Holcomb, Efficient PUF-Based Key Generation in FPGAs using Per-Device Configuration, in IEEE Transactions on VLSI Systems, vol. 27, no. 2, February 2019, pp. 364-375. 
  
• N. K. Dumpala, S. B. Patil, D. Holcomb, and R. Tessier, Loop Unrolling for Energy Efficiency in Low-Cost FPGAs, in ACM Transactions on Reconfigurable Technology and Systems, vol. 11, no. 4, January 2019, pp. 26:1-26:23. 
  
• M. Fyrbiak, S. Wallat, J. Dechelotte, N. Albartus, S. Bocker, R. Tessier and C. Paar, On the Difficulty of FSM-based Hardware Obfuscation, in IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2018, no. 3, September 2018, pp. 293-330. 
  
• M. Fyrbiak, S. Rokicki, N. Bissantz, R. Tessier, and C. Paar, Hybrid Obfuscation to Protect against Disclosure Attacks on Embedded Microprocessors, in IEEE Transactions on Computers, vol. 67, no. 3, March 2018, pp. 307-321. 
  
• V. Migliore, C. Seguin, M. M. Real, V. Lapotra, A. Tisserand, C. Fontaine, G. Gogniat, and R. Tessier, A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm, in ACM Transactions on Embedded Computing Systems, vol. 16, no. 5, October 2017, pp. 138:1-138:17. 
  
• K. Hu, H. Chandrikakutty, Z. Goodman, R. Tessier, and T. Wolf, Dynamic Hardware Monitors for Network Processor Protection, in IEEE Transactions on Computers, vol. 65, no. 3, March 2016, pp. 860-872. 
  
• T. Wolf, H. Chandrikakutty, K. Hu, D. Unnikrishnan, and R. Tessier, Securing Network Processors with High-Performance Hardware Monitors, in IEEE Transactions on Dependable and Secure Computers, vol. 12, no. 6, December 2015, pp. 652-664. 
  
• R. Tessier, K. Pocek, and A. DeHon, Reconfigurable Computing Architectures, in Proceedings of the IEEE, vol. 103, no. 3, March 2015, pp. 332-354. 
  
• J. Lu, R. Tessier and W. Burleson, Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 6, June 2014, pp. 853-866. 
  
• D. Unnikrishnan, R. Vadlamani, Y. Liao, J. Crenne, L. Gao and R. Tessier, Reconfigurable Data Planes for Scalable Network Virtualization, in IEEE Transactions on Computers, vol. 62, no. 12, December 2013, pp. 2476-2488. 
  
• J. Lu, P. Siqueira, V. Vijayendra, H. Chandrikakutty, and R. Tessier, Real-Time Differential Signal Phase Estimation for Space-based Systems Using FPGAs, in IEEE Transactions on Aerospace and Electronic Systems, vol. 49, no. 2, April 2013, pp. 1192-1209. 
  
• J. Crenne, R. Vaslin, G. Gogniat, J.-P. Diguet, R. Tessier and D. Unnikrishnan, Configurable Memory Security in Embedded Systems, in ACM Transactions on Embedded Computer Systems, vol. 12, no. 3, March 2013, pp. 1-25. 
  
• J. Zhao, S. Madduri, R. Vadlamani, W. Burleson, and R. Tessier, A Dedicated Monitoring Infrastructure For Multicore Processors, in IEEE Transactions on VLSI Systems, vol. 19, no. 6, June 2011, pp. 1011-1022. 
  
• T. Wolf, R. Tessier, and G. Prabhu, Securing the Data Path of Next-Generation Router Systems, in Computer Communications, vol. 31, no. 4, April 2011, pp. 598-606. 
  
• D. Yin, D. Unnikrishnan, Y. Liao, L. Gao, and R. Tessier, Customizing Virtual Networks with Partial FPGA Reconfiguration, in ACM Computer Communication Review, January 2011, vol. 41, no. 1., January 2011, pp. 125-132. 
  
• W. Xu and R. Tessier, Tetris-XL: A Performance-Driven Spill Technique for Embedded VLIW Processors, in ACM Transactions on Architecture and Code Optimization, vol. 6, no. 3, September 2009, pp. 1-40. 
  
• R. Vaslin, G. Gogniat, J.-P. Diguet, E. Wanderley, R. Tessier and W. Burleson, A Security Approach for Off-Chip Memory in Embedded Microprocessor Systems, in Journal of Microprocessors and Microsystems, vol. 33, no. 1, February 2009, pp. 37-45. 
  
• I. Kuon, R. Tessier, and J. Rose, FPGA Architecture: Survey and Challenges, in Foundations and Trends in Electronic Design Automation, vol. 2, no. 2, 2008, pp. 135-253. 
  
• R. Tessier, Multi-FPGA Systems: Logic Emulation, in Reconfigurable Computing, Morgan-Kaufmann, S. Hauck and A. DeHon, ed., 2008, pp. 637-670.
  
• R. Tessier, V. Betz, D. Neto, A. Egier, and T. Gopalsamy, Power Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, Feb. 2007, pp. 278-290.  
  
• P. Menon, W. Xu, and R. Tessier, Design-Specific Path Delay Testing in Lookup Table-based FPGAs, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, May 2006, pp. 867-877.  
  
• R. Tessier, D. Jasinski, A. Maheshwari, A. Natarajan, W. Xu, and W. Burleson, An Energy-Aware Active Smart Card, in IEEE Transactions on VLSI Systems, vol. 13, no. 10, Oct. 2005, pp. 1190-1199.  
  
• R. Tessier, S. Swaminathan, R. Ramaswamy, D. Goeckel, and W. Burleson, A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder, in IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488.  
  
• J. Liang, A. Laffely, S. Srinivasan, and R. Tessier, An Architecture and Compiler for Scalable On-Chip Communication, in IEEE Transactions on VLSI Systems, vol. 12, no. 7, July 2004, pp. 711-726.  
  
• G. Farquharson, W. Junek, A. Ramanathan, S. Frasier, R. Tessier, D. McLaughlin, M. Sletten, and J. Toporkov, A Pod-Based Dual-Beam InSAR, in IEEE Transactions on Geoscience and Remote Sensing Letters, vol 1, no. 2, April 2004, pp. 62-65.  
  
• A. Maheshwari, W. Burleson, and R. Tessier, Trading Off Transient Fault-tolerance and Power Consumption in Deep Submicron VLSI Circuits, in IEEE Transactions on VLSI Systems, vol 12, no. 3, March 2004, pp. 299-311.  
  
• P. Jain, A. Laffely, W. Burleson, R. Tessier, and D. Goeckel, Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations, in Journal of VLSI Signal Processing, vol 36, no. 1, January 2004, pp. 27-40.  
  
• S. Krishnamoorthy and R. Tessier, Technology Mapping Algorithms for Hybrid FPGAs Containing Lookup-Tables and PLAs, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 22, no. 5, May 2003, pp. 545-559.  
  
• I. G. Harris and R. Tessier, Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 21, no. 11, November 2002, pp. 1337-1343.  
  
• M. Kudlugi and R. Tessier, Static Scheduling of Multi-domain Circuits for Fast Functional Verification, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 21, no. 11, November 2002, pp. 1253-1268.  
  
• R. Tessier and S. Jana, Incremental Compilation for Parallel Logic Verification Systems, in IEEE Transactions on VLSI Systems, vol 10, no. 5, October 2002, pp 623-636.  
  
• N. Vemuri, P. Kalla, and R. Tessier, BDD-Based Logic Synthesis for LUT-Based FPGAs, in ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 4, October 2002, pp 501-525.  
  
• R. Tessier, Fast Placement Approaches for FPGAs, in ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 2, April 2002, pp 284-305.  
  
• R. Tessier and W. Burleson, Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future, in Programmable Digital Signal Processors, Yu Wen Hu, ed., Marcel Dekker, pp. 147-186, 2002.
  
• R. Tessier and W. Burleson, Reconfigurable Computing and Digital Signal Processing: A Survey, in Journal of VLSI Signal Processing, May/June 2001, pp. 7-27.  
  
• J. Babb, R. Tessier, M. Dahl, S. Hanano, D. Hoki, and A. Agarwal, Logic Emulation with Virtual Wires, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1997.