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Preliminary Program

Sunday – June 24th

All events (except the banquet) will take place in the Campus Center - Campus Hotel Bldg.


19:00 – 21:00

Welcome Reception
In the BlueWall (entrance floor of the campus center Bldg.) - use the entrance near the Book Store.

Monday – June 25th

08:30 – 09:00 Registration


09:00 – 09:15

Welcome and introduction
Campus Center, room 163 (take the escalator to the floor below)

09:15 – 10:15

Keynote talk: Accelerated Computing on POWER Platform
Balaram Sinharoy, IBM Fellow

10:15 – 10:45 Coffee break

10:45 – 12:00 – Session 1: Multiplication and Fused-Multiply-Add
Chair: Vojin Oklobdzija


10:45 – 11:10

High Density and Performance Multiplication for FPGA
Martin Langhammer and Gregg Baeckler

11:10 – 11:35

Karatsuba with Rectangular Multipliers for FPGAs
Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes
Kappauf and Peter Zipf

11:35 – 12:00

A Correctly Rounded Mixed-Radix Fused-Multiply-Add
Clothilde Jeangoudoux and Christoph Lauter

12:00 – 13:30 Lunch - BlueWall Cafeteria

13:30 – 14:45 Special Session: Arithmetic for Artificial Intelligence and Machine Learning
Chair: Eric Schwarz


13:30 – 13:55

Flexpoint: Predictive Numerics for Deep Learning
Valentina Popescu, Marcel Nassar, Xin
Wang, Evren Tumer, and Tristan Webb

13:55 – 14:20

FPGA Machine Learning Datapaths
Martin Langhammer

14:20 – 14:45

Efficient Arithmetic for Deep Learning
Stuart Oberman

14:45 – 15:15 Coffee break

15:15 – 16:05 Session 2: Accelerators for Artificial Intelligence and Machine Learning
Chair: Milos Ercegovac


15:15 – 15:40

Tunable Floating-Point for Energy Efficient Accelerators
Alberto Nannarelli

15:40 – 16:05

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip
Mantas Mikaitis, Dave Lester, Delong Shang, Steve Furber, Gengting Liu, Jim Garside,
Stefan Scholze, Sebastian Höppner and Andreas Dixius

16:15 – 17:15 Panel: Arithmetic requirements for AI and Deep Learning
Moderator: Eric Schwarz

18:00 – 19:00 IEEE 754 working group meeting
Room 902 in the Campus center - UMass Hotel Bldg.

18:30 – 20:00 Dinner in the Hampshire Dining Commons

Tuesday – June 26th

09:00 – 09:50 Special Session: IEEE Standard 754-2018 and Future Plans
Chair: Marius Cornea


09:00 – 09:25

What is coming in the IEEE Standard 754 – 2018
David Hough

09:25 – 09:50

Plans for IEEE Standard 754 – 2028
Jason Riedy

09:55 – 10:45 Session 3: Accurate computation
Chair: David Hough


09:55 – 10:20

Augmented Arithmetic Operations Proposed for IEEE-754 2018
Jason Riedy and James Demmel

10:20 – 10:45

On various ways to split a floating-point Number
Claude-Pierre Jeannerod, Jean-Michel Muller and Paul
Zimmermann

10:45 – 11:15 Coffee break

11:15 – 12:30 Session 4: Floating-point
Chair: Stuart Oberman


11:15 – 11:40

VeriTracer: Context-enriched tracer for floating-point arithmetic analysis
Yohan Chatelain, Pablo De Oliveira Castro, Eric Petit, David Defour,
Jordan Bieder and Marc Torrent

11:40 – 12:05

A Formally-Proved Algorithm to Compute the Correct Average of Decimal Floating-Point Numbers
Sylvie Boldo, Florian Faissole and Vincent Tourneur

12:05 – 12:30

FP-ANR: A representation format to handle floating-point cancellation at run-time
David Defour

12:30 – 14:00 Lunch - BlueWall Cafeteria

14:00 – 14:50 Session 5: Division
Chair: Alberto Nannarelli


14:00 – 14:25

Radix-64 Floating-Point Divider
Javier D. Bruguera

14:25 – 14:50

Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
Weiqiang Liu, Jing Li, Tao Xu, Chenghua Wang, Paolo Montuschi and Fabrizio Lombardi

14:50 – 15:40 Session 6: Function evaluator and numerical solver
Chair: Sylvie Boldo


14:50 – 15:15

A High Throughput Polynomial and Rational Function Approximations Evaluator
Nicolas Brisebarre, George Constantinides, Milos Ercegovac, Silviu-Ioan Filip, Matei Istoan
and Jean-Michel Muller

15:15 – 15:40

Digit Elision for Arbitrary-accuracy Iterative Computation
He Li, James Davis, John Wickerson and George Constantinides

15:40 – 16:10 Coffee Break

16:10 – 17:10 Panel: Future Directions in Computer Arithmetic
Moderator: Paolo Montuschi
       Milos Ercegovac, David Matula and Jean-Michel Muller

17:30 Board Buses

18:00-21:30 Banquet at the Log Cabin (500 Easthampton Road, Holyoke, MA 01040)

Wednesday – June 27th

09:00 – 10:15 Session 7: Industry track – SIMD operations
Chair: Elisardo Antelo


09:00 – 09:25

Fast multiplication of binary polynomials with the forthcoming vectorized VPCLMULQDQ instruction
Nir Drucker, Shay Gueron and Vlad Krasnov

09:25 – 09:50

Enhanced Vector Math Support on the Intel® AVX-512 Architecture
Cristina Anderson, Jingwei Zhang and Marius Cornea

09:50 – 10:15

The comeback of Reed Solomon codes
Nir Drucker, Shay Gueron and Vlad Krasnov

10:15 – 10:45 Coffee Break

10:45 – 12:00 Session 8: Modular operations and Cryptography
Chair: Martin Langhammer


10:45 – 11:10

Faster Modular Exponentiation using Double Precision Floating Point Arithmetic on the GPU
Niall Emmart, Fangyu Zheng and Charles Weems

11:10 – 11:35

A New Variant of the Barrett Algorithm Applied to Quotient Selection
Niall Emmart, Fangyu Zheng and Charles Weems

11:35 – 12:00

New Area Record for the AES Combined SBox/Inverse SBox
Arash Reyhani, Mostafa Taha and Doaa Ashmawy

12:00 – 12:10 Closing

12:15 Lunch - BlueWall Cafeteria

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