This work is motivated by the
increasing importance of on-chip monitoring in modern processors. As
silicon processes scale, on-chip system will require multiple
monitors that performs assessment of performance, security, and physical
characteristics that change during the operation of a device. The
parameters that can be monitored include temperature, voltage, processor
activity and power supply fluctuation, etc. It is expected that future
on-chip systems will generally include numerous embedded monitors. These
monitors speed up the computation of environmental monitoring compared
to software execution. They provide quickly system performance
evaluation without interfering with the primary operation of the system.
They provide tradeoffs in terms of throughput, area, latency,
reliability, power and energy in order to meet real time constraints.
Our monitoring-based approach requires the integration of multiple
monitors to form a complete chip subsystem devoted to monitoring.
main aspect of the work involves the architectural definition of
configurable monitors, lightweight components which can collect and
potentially evaluate data from each target core or sensor. A second key
feature of our approach is a low-latency monitor network-on-chip which
interconnects the on-chip monitors and transmit monitor packet with low
latency. Data collected from the multiple monitors via the network are
collated by a programmable monitor executive processor (MEP). In
response to abnormal behavior, the MEP can issue commands to control the
operation of the on-chip system. For example, it can override the power
management, disable I/O operations, or throttle voltage/frequency. The
integration of the monitors and associated network requires system level
validation via architectural and circuit-level simulation. A
communication protocol is developed to allow for priority-driven data
transfer of monitor data to the MEP.
This work is funded by Semiconductor Research
Corporation under Task 1595.001.
J. Zhao, W. Burleson and R.
Tessier, Distributed Sensor Data Processing for Many-cores, in the
Proceedings of the ACM Great Lakes Symposium on VLSI, Salt Lake City, UT, May 2012.
J. Zhao, S. Madduri, R. Vadlamani, W. Burleson
and R. Tessier, A Dedicated Monitoring Infrastructure for Multicore Processors,
in IEEE Transactions on Very Large Scale Integration
Systems, vol. 19, no. 6, June 2011, pp. 1011-1022.
J. Zhao, B. Datta, W. Burleson
and R. Tessier, Thermal-aware Voltage Droop Compensation for Multi-core Architectures,
in the Proceedings of the ACM Great Lakes Symposium on VLSI, Providence,
RI, May 2010.
R. Vadlamani, J. Zhao, W. Burleson
and R. Tessier, Multicore Soft Error Rate Stabilization Using
Adaptive Dual Modular Redundancy, in the Proceedings of the IEEE/ACM
Design Automation and Test in Europe Conference, Dresden, Germany, March
S. Madduri, R. Vadlamani, W.
Burleson and R. Tessier, A Monitor Interconnect and Support Subsystem
for Multicore Processors, in the Proceedings of the IEEE/ACM Design
Automation and Test in Europe Conference, Nice, France, April 2009.