Design mapping for logic emulation often requires many hours of compilation time. The most time consuming part of the process is the compilation of tens or hundreds of individual logic processors (FPGAs). In this work, we attempt to minimize logic emulation design re-mapping time for small design changes. Rather than recompiling all FPGAs from scratch, only affected resources are identified and recompiled. We have demonstrated that compile time can be reduced by up to an order of magnitude for design changes ranging from 5 to 15% of the total design. Our approach has been demonstrated on an Ikos VirtuaLogic VLE-2M emulator containing 128 Xilinx XC4036 FPGAs.

In most contemporary multi-FPGA logic emulators, communication between multiple FPGAs and between FPGAs and on-board memories is scheduled so that FPGA pin and board routing resources may be reused over time. To guarantee accurate results, scheduling is generally performed in reference to the design clock of the emulated design clock. The presence of multiple design clock domains, which have no phase relationship, can make communication scheduling difficult. Our approach to multi-domain scheduling isolates scheduling to individual domains and provides constraints for inter-domain interaction

Multi-FPGA logic emulators often contain hundreds of individual FPGAs. Due to dependencies, during design emulation, only a fraction of design logic and interconnect is active. In our Virtual Wires approach to emulation, inter-FPGA logic dependencies are analyzed and logic evaluation and inter-FPGA signal communication is scheduled. This approach overcomes FPGA pin limitations by reusing pin resources over time in a time-sliced fashion. In recent work, we interface SystemC, a C-based hardware description language, to an Ikos VirtuaLogic VLE-2M emulator, which is based on the Virtual Wires approach.