DE4 NetFPGA

Reference Router Architecture

  • NetFPGA Reference Router Architecture - Describes the architecture of the reference router.

    • NetFPGA Reference Router Architecture

    The NetFPGA reference router is a complete IPv4 router which is able to simultaneously forward packets from all four 1 Gbps interfaces on the NetFPGA card. As seen in Figure, the main components of the reference router include input queues (RxQ), an arbiter which selects packets from a specific input queue, an output port lookup, and interfaces to output queues (TxQ). The output port lookup requires an access to a forwarding table which indicates the packet destination based on information in the packet header. A detailed overview of the reference router architecture can be found at NetFPGA.

  • DE4 Reference Router Architecture - Describes the architecture of the DE4 NetFPGA reference router.

    • DE4 Reference Router Architecture

    The DE4 reference router is implemented on a SOPC based builder system which provides easy integration of different interfaces to the FPGA fabric. The reference router is integrated along with this SOPC builder as illustrated in the Figure below. The MAC queues connect to the Gigabit Ethernet Interface and the CPU queues connect to the PCI Express interface through the SOPC builder. The onboard Marvell Gigabit Ethernet transceiver and Triple Speed Ethernet MAC processes Network packets through the Gigabit Ethernet Interface. The PCI Express Interface provides a DMA engine for sending packets from the host machine through the PCI Express link. The JTAG interface provides an alternate interface for configuring the registers on the FPGA and also for debugging the design. A detailed overview of the reference router can be found at NetFPGA.

DE4 Reference Router Walk Through

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