Maciej Ciesielski

Professor

University of Massachusetts
Department of Electrical & Computer Engineering
309B Knowles Engineering Building
Amherst , MA 01003

Tel: (413) 545-0401, Fax: (413) 545-1993
Email: ciesiel@ecs.umass.edu
http://www.ecs.umass.edu/ece/labs/vlsicad/ciesiel.html

Other faces of Prof. Ciesielski ....

Biography/CV (pdf)

• Ph.D., University of Rochester 1984.
• M.S., Warsaw Technical University, 1974

• 1986-present, University of Massachusetts, Amherst.
• 1983-1986, GTE Laboratories, Waltham, MA;

• Formal verification and design validation.
• Behavioral and logic synthesis from high-level specifications.
• Physical design automation, layout synthesis.
• Mathematical optimization.

Publications and Slides

A set of selected research papers and over 400 PowerPoint presentation slides and tutorials.

Software Releases

• TEDify is a CAD software to generate and optimize Taylor Expansion Diagrams (TED), a novel, canonical, graph-based representation for arithmetic expressions of data flow designs. In addition to equivalence checking of high-level design specifications, TEDs can be used for optimization of mathematical expressions derived from DSP designs and other high-level design descriptions. TED adds behavioral transformation level to architectural and RTL synthesis.
  • High Level Transformations using TEDs project and the TED package demonstrated at the University Booth at DATE 2006 conference.
  • Download TEDify package.
  This project was supported by the National Science Foundation under Grant No. CCR-0204146.

• BDS (BDD-based Logic Synthesis system) is our fast and efficient logic synthesis tool, based on a novel theory of BDD-based bi-decomposition. It provides both algebraic and Boolean decomposition of several types: AND, OR, XOR, and MUX. It handles random and control logic (AND-OR intensive) functions as well as arithmetic (XOR-intensive) functions. Its unique approach to partitioned BDD's allows it to handle very large circuits. Version BDS-1.2 is now available from the following link: <
  • Download BDS package.
  This project has been supported by the National Science Foundation under Grant No. 9901254.

Graduate Students

• Daniel Gomez-Prado (Ph.D.) - Behavioral verification and synthesis.
  
• Dusung Kim (Ph.D.) - Verification and simulation of Systems on Chip.
  

Teaching:

• Spring 2008: On sabbatical
  
  • Ecole Polytechnique Fédérale de Lausanne, Switzerland; Université de Bretagne Sud, Lorient, France; Université de Montpellier, France.

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• Fall 2007: ENGIN 112 - Introduction to Electrical & Computer Engineering
  

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• Spring 2007: ECE 667 - Synthesis and Verification of Digital Designs
  

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• Fall 2006: ENGIN 112 - Introduction to Electrical & Computer Engineering
• Fall 2006: ECE 353 - Computer Systems Lab I
  

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• Spring 2006: ECE 697b - Synthesis and Verification of Digital Designs
  

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About Group, Department and University:

• Department of Electrical and Computer Engineering
• University of Massachusetts