Maciej Ciesielski
Professor
Tel: (413) 545-0401,
Fax: (413) 545-1993
Email: ciesiel@ecs.umass.edu
http://www.ecs.umass.edu/ece/labs/vlsicad/ciesiel.html
Biography/CV (pdf)
EDUCATION
- Ph.D., University of Rochester, 1984.
- M.S., Warsaw Technical University, 1974
EMPLOYMENT
- 1986-present, University of Massachusetts, Amherst.
- 1983-1986, GTE Laboratories, Waltham, MA;
AWARDS
RESEARCH ACTIVITIES
Electronic Design Automation (EDA): CAD tools and algorithms.
- Formal verification; functional verification of arithmetic circuits.
- Simulation-based design validation; parallel simulation.
- Behavioral and logic synthesis from high-level specifications.
- Mathematical optimization.
Lab affiliation:
VLSI CAD Laboratory
Publications and Slides
A set of selected research papers
and over 400 PowerPoint
presentation slides and tutorials.
Software Releases
-
TDS system
is an experimental software tool to perform behavioral transformations of designs specified on algorithmic and behavioral levels. TDS transforms the initial design specifications into a data flow graph (DFG) optimized for a particular objective (latency, resource utilization, etc.) prior to high-level synthesis. The behavioral transformations are based on graph-based canonical representation, Taylor Expansion Diagram (TED), followed by structural transformations of the resulting DFG network.
Thanks to canonicity of the TED representation, the system can be also used for equivalence checking of designs specified in C or behavioral HDL.
The system is intended for data-flow and computation-intensive designs used in digital signal processing applications.
This project was supported by the National Science Foundation under
award No. CCR-0204146 and CCR-0702506 and was done in collaboration with Lab-STICC, Université de Bretagne Sud, Lorient, France.
- BDS (BDD-based Logic Synthesis system)
is our fast and efficient logic synthesis tool, based on a novel theory
of BDD-based bi-decomposition.
It provides both algebraic and Boolean decomposition of several types:
AND, OR, XOR, and MUX.
It handles random and control logic (AND-OR intensive) functions
as well as arithmetic (XOR-intensive) functions.
Its unique approach to partitioned BDD's allows it to handle very large
circuits. Version BDS-1.2 is now available from the following link:
<
This project has been supported by the National Science Foundation under
grant No. 9901254.
Graduate Students
-
Daniel Gomez-Prado (Ph.D.) - Behavioral synthesis and verification.
-
Tariq Ahmed (Ph.D.) - Parallel simulation and formal verification.
-
Priyanka Gopalakrishna (MS) - Functional verification of arithmetic circuits.
-
Girish Paladugu (MS) - Parallel simulation.
-
Dusung Kim (Ph.D.) - Design validation and simulation of Systems on Chip.
Graduated Nov. 2011. Now at Synopsys, Santa Clara, CA
-
Mohamed Abdul Basith (MS) - Formal verification of arithmetic circuits.
Graduated August 2011. Now at LSI Corporation.
Teaching:
About Group, Department and University: