SLIDES (very old, new slides under construction ... )
Tutorials, conference, and miscellaneous PowerPoint presentations:

These slides can be used and distributed for educational purposes, provided that you properly credit their source. Your comments and feedback will be greatly appreciated.

• C. Yu, T. Su, A. Yasin, M. Ciesielski Spectral Approach to Verification of Nonlinear Arithmetic Circuit , ASPDAC, Tokyo 2019.

• M. Ciesielski Functional Verification of Arithmetic Circuits , ICCD 2015 Tutorial.

• Z. Zeng, Q. Zhang, I. Harris, M. Ciesielski, Fast Compputation of Data Correlation using BDDs , (16 slides), Design Automation & Test in Europe, DATE-2003.

• P. Kalla, M. Ciesielski, E. Boutillon, E. Martin, High-Level Design Verification using Taylor Expansion Diagrams: First Results , HLDVT-02 (16+) slides.

• M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification , (30 slides, 335kB), Design Automation & Test in Europe, DATE-2002.

• M. Ciesielski, Binary Decision Diagrams (BDDs) - Tutorial , Slides showing the construction of and basic operation on BDDs (17 slides, 165 kB)

• M. Ciesielski, TUTORIAL: Formal Methods in Hardware Verification , (96 slides, 682kB), LIRMM, 2000/2001.

• Z. Zeng, P. Kalla, M. Ciesielski, LPSAT: A Unified Approach to RTL Satisfiability , (25 slides, 670kB), Design, Automation and Test in Europe Conference, DATE-2001.

• Z. Zeng, M. Ciesielski, B. Rouzeyre, Functional Test Generation using Constraint Logic Programming , (26 slides, 160kB), IFIP VLSI-SOC Conference VLSI-SOC'2001.

• C. Yang, M. Ciesielski, BDS: A BDD-based Logic Optimization System (34 slides, 440kB) - based on Ph.D. thesis of C. Yang, 1999.

• M. Ciesielski, TUTORIAL: Synthesis for Pass Transistor Logic (PTL) , (30 slides, 440kB), ISEP, 2000.

• C. Yang, M. Ciesielski, Synthesis for Mixed CMOS/PTL Logic , (12 slides, 260kB) Design, Automation and Test in Europe Conference, DATE-2000.

• S. Askar, M. Ciesielski, Transistor Placement for Custom Datapath Design , (44 slides, 990kB) - based on M.S. thesis of S. Askar, 2000.

• P. Kalla, M. Ciesielski, A BDD-based Satisfiability using the Unate Recursive Paradigm , (10 slides, 112kB) Design, Automation and Test in Europe Conference, DATE-2000.