Synopsys^TM

Behavioral Compiler

Use sold for official help

Online quick Behavioral Compiler references:

http://www.synopsys.com/products/beh_syn/beh_syn.html

http://kahuna.sdsu.edu/~hansson/Behavioral_syn_Report.htm

http://users.ece.gatech.edu/celebi/project/part1/bcreview.htm

A simple design from hyperlink2(http://kahuna..),I wrote a script file for it. This example is designed to introduce you to familiar with the Synopsys^TM Behavioral Compiler.

1. Download this design example.vhd to your account.

2. Download script example.scr to your account.

3. Run the following command in your account:

example> dc_shell -f example.scr;

Warning: Sucessful running requires target library;here I use typical.db from TSMC, put typical.db in your work directory, or reconfigure compile.scr

4. If everything work right,there should be four files generated in your directory :

Database file for logic synthesis: example_sch_rtl.db

HDL file for logic synthesis: example_sch_rtl.v

HDL file for simulation ONLY: example_sch_rtl_sim.v

Results of Behavioral Compiler scheduling and allocation example.rpt

5. To view graphically how your design looks like after scheduling and allocation.

example> design_analyzer&

6.In the window that comes up,select Setup-> Command Window-->input: read example_sch_rtl.db --->double click exampel icon in Design Analyzer window

7. For logic synthesis, refer to Design Compiler