/**************************************
* Synopsys BC Script
* Schedule mode : Superstate fixed
* Date 2/4/02
* Ning Weng

Input :  Technology file: typical.db;  design: example.vhd
Output:  1. Scheduled and constrained database file for logic syntheis:
            example_sch_rtl.db
	 2. Scheduled and constrained hdl file for logic synthesis:
	    example_sch_rtl.v
	 3. Scheduled and constrained hdl file for simulation ONLY: 	 
	    example_sch_rtl_sim.v
	 4. Reports the results of Behaviral Compiler scheduling and allocation:
	    example.rpt	

useage: example>dc_shell -f example.scr
**************************************/

/*set to be true to view the results graphically*/
bc_enable_analysis_info = true

/*set a temp working directory to make main directory neat*/
sh "rm -r work"
sh "mkdir work"
define_design_lib work -path work 

/* Analyzing and Elaborating design*/

link_library = {"*" typical.db}
read -f db typical.db
target_library ={typical.db}

analyze -format vhdl -lib work example.vhd
elaborate -schedule example 

/* create clock*/
create_clock clk -name CLK  -period 10

/* calculates the timing and area estimate for the design*/
bc_time_design

/*reports the timing and area estimates, must after bc_time_design*/
report_resource_estimates


/* schedule to invoke the scheduling and allocation functions of 
behavioral compiler, which determines the minimum number of clock cycles 
using the fewest resources.*/
schedule -io su -eff med

/* After satisfied with the results of scheduling, write RTL.db file and 
HDL format*/

/*1.RTL.db is a scheduled and constrained database file you can use for 
logic synthesis*/

write -hierarchy -output  example_sch_rtl.db

/*2.write a rtl description of design generated by bc*/

write_rtl -format verilog -output example_sch_rtl.v 

/*3.write a scheduled design to HDL format file optimized for simulation*/
write_rtl -format verilog -simulation -output example_sch_rtl_sim.v

/*report_schedule reports the results of Behavioral Compiler scheduling 
and allocation*/

report_schedule -var -op -summ -a >example.rpt

/*here you are ready to performs logic-level synthesis and optimization,
starting from read in the previously save .db file and compile it, for
detail reference Design Compiler */

quit