Synopsys^TM

Design Compiler

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Very simple example: 10bit Adder. This example is designed to introduce you to the Synopsys^TM Design Compiler.

1. Download this design add10x10.v to your account

2. Download synthesis script compile.scr to your account

3. Run the following command in your account

example> dc_shell -f compile.scr;

Warning: Sucessful running requires target library;here I use typical.db from TSMC, put typical.db in your work directory, or reconfigure compile.scr. This will produce your gate-level design named add10x10_syn.v in your account.

Comment: Better understand the compile script file is critical . Engineer normally love script than mouse- clicking, however, if you want to see how colorful you design are..go step 4

4. Run the following command in your account

example> design_analyzer&

5.In the window that comes up,select Setup-> Command Window...

6.Copy and paste compile.scr line by line to Command Window. Pay attention to Command Widow and Designa Analyzer Window

7. Gate-Level netlist add10x10_syn.v in your account

8. Analysis report.out in your account. If this file is not in your account, from the Synopsys Design Analyzer -->Analysis-->Report--> choose Send Output To File

Comment2: Instead of like step 4 debugging line by line, you can choose execute script file(From Design Analyzer Window--> Setup-->Execute Script)