***************************************************************************
               Date      : Tue Feb  5 03:58:02 2002
               Version   : 2000.11-SP1
               Design    : example
***************************************************************************

*************************************
*  Register usage of process main:  *
*************************************

	Storage resource types
======================
    r262......32-bit register 
    r820......32-bit register 



-------+------+------
 cycle | r820 | r262 
----------------------
       | (32) | (32) 
======================
   0   |......|......
   1   |..v0..|..v1..
   2   |......|......
   3   |......|......


	Data value name abbreviations
======================
    v0......32-bit data value reset_loop/algorithm_loop/mul_40/mult_40/Z
    v1......32-bit data value reset_loop/algorithm_loop/mul_40/mult_40_2/Z


*****************************************
*  Operation schedule of process main:  *
*****************************************

	Resource types
====================================
    a.........16-bit input port 
    b.........16-bit input port 
    c.........16-bit input port 
    d.........16-bit input port 
    e.........16-bit input port 
    f.........16-bit input port 
    loop......loop boundaries 
    r221......(16_16->16)-bit DW01_sub 
    r229......(32_32->32)-bit DW01_add 
    r234......(32_32->32)-bit DW01_add 
    r238......(16_16->32)-bit DW02_mult 
    r758......(16_16->32)-bit DW02_mult 
    y.........32-bit registered output port 



                                                                                D      D        
                                                           D      D      D      W      W        
                                                           W      W      W      0      0        
                                                           0      0      0      2      2        
                                                           1      1      1      _      _        
                 p      p      p      p      p      p      _      _      _      m      m     p  
                 o      o      o      o      o      o      a      a      s      u      u     o  
                 r      r      r      r      r      r      d      d      u      l      l     r  
                 t      t      t      t      t      t      d      d      b      t      t     t  
-------+------+-----+------+------+------+------+------+------+------+------+------+------+-----
 cycle | loop |  a  |  b   |  c   |  d   |  e   |  f   | r234 | r229 | r221 | r238 | r758 |  y  
-------------------------------------------------------------------------------------------------
   0   |..L3..|.....|......|......|......|......|......|......|......|......|......|......|.W32.
       |..L0..|.....|......|......|......|......|......|......|......|......|......|......|.....
   1   |..L6..|.R40.|.R40a.|......|.R40c.|.R40d.|.R40e.|......|......|.o40d.|.o40b.|.o40c.|.....
   2   |......|.....|......|.R40b.|......|......|......|.o40..|.o40a.|......|......|......|.W40.
   3   |..L8..|.....|......|......|......|......|......|......|......|......|......|......|.....
       |..L7..|.....|......|......|......|......|......|......|......|......|......|......|.....
       |..L5..|.....|......|......|......|......|......|......|......|......|......|......|.....
       |..L4..|.....|......|......|......|......|......|......|......|......|......|......|.....
       |..L2..|.....|......|......|......|......|......|......|......|......|......|......|.....
       |..L1..|.....|......|......|......|......|......|......|......|......|......|......|.....


	Operation name abbreviations
=============================
    L0........loop boundaries main_design_loop_begin
    L1........loop boundaries main_design_loop_end
    L2........loop boundaries main_design_loop_cont
    L3........loop boundaries reset_loop/reset_loop_design_loop_begin
    L4........loop boundaries reset_loop/reset_loop_design_loop_end
    L5........loop boundaries reset_loop/reset_loop_design_loop_cont
    L6........loop boundaries reset_loop/algorithm_loop/algorithm_loop_design_loop_begin
    L7........loop boundaries reset_loop/algorithm_loop/algorithm_loop_design_loop_end
    L8........loop boundaries reset_loop/algorithm_loop/algorithm_loop_design_loop_cont
    R40.......16-bit read reset_loop/algorithm_loop/a_40
    R40a......16-bit read reset_loop/algorithm_loop/b_40
    R40b......16-bit read reset_loop/algorithm_loop/c_40
    R40c......16-bit read reset_loop/algorithm_loop/d_40
    R40d......16-bit read reset_loop/algorithm_loop/e_40
    R40e......16-bit read reset_loop/algorithm_loop/f_40
    W32.......32-bit write reset_loop/y_32
    W40.......32-bit write reset_loop/algorithm_loop/y_40
    o40.......(32_32->32)-bit ADD_UNS_OP reset_loop/algorithm_loop/add_40/plus_40
    o40a......(32_32->32)-bit ADD_UNS_OP reset_loop/algorithm_loop/add_40/plus_40_2
    o40b......(16_16->32)-bit MULT_UNS_OP reset_loop/algorithm_loop/mul_40/mult_40
    o40c......(16_16->32)-bit MULT_UNS_OP reset_loop/algorithm_loop/mul_40/mult_40_2
    o40d......(16_16->16)-bit SUB_UNS_OP reset_loop/algorithm_loop/sub_40/minus_40


***************************************************************************
***************************************************************************
               Date      : Tue Feb  5 03:58:02 2002
               Version   : 2000.11-SP1
               Design    : example
***************************************************************************

**************************************
*  Summary report for process main:  *
**************************************
---------------------------------------------------------------------------
     Timing Summary
---------------------------------------------------------------------------
 Clock period 10.00
 Loop timing information:
    main............................................3 cycles (cycles 0 - 3)
        reset_loop..................................3 cycles (cycles 0 - 3)
            algorithm_loop..........................2 cycles (cycles 1 - 3)
---------------------------------------------------------------------------
     Area Summary
---------------------------------------------------------------------------
 Estimated combinational area    105203
 Estimated sequential area       10309
 TOTAL                           115512

 4 control states
 4 basic transitions
 2 control inputs
 2 control outputs

---------------------------------------------------------------------------
     Resource types
---------------------------------------------------------------------------
	Register Types
========================================
	32-bit register....................2

	Operator Types
========================================
	(16_16->16)-bit DW01_sub...........1
	(16_16->32)-bit DW02_mult..........2
	(32_32->32)-bit DW01_add...........2

	I/O Ports
========================================
	16-bit input port..................6
	32-bit registered output port......1

---------------------------------------------------------------------------
***************************************************************************
               Date      : Tue Feb  5 03:58:02 2002
               Version   : 2000.11-SP1
               Design    : example
***************************************************************************

************************************************
*  State graph style report for process main:  *
************************************************
===========================================================================
 present  	 next
 state	input	 state		actions
---------------------------------------------------------------------------
 s_0_0	 c1	 s_1_1	 a_7	 reset_loop/y_32 (write)
 s_1_1	 c2	 s_2_2	 a_0	 reset_loop/algorithm_loop/a_40 (read)
			 a_1	 reset_loop/algorithm_loop/b_40 (read)
			 a_3	 reset_loop/algorithm_loop/d_40 (read)
			 a_4	 reset_loop/algorithm_loop/e_40 (read)
			 a_5	 reset_loop/algorithm_loop/f_40 (read)
			 a_15	 reset_loop/algorithm_loop/mul_40/mult_40 (operation)
			 a_18	 reset_loop/algorithm_loop/mul_40/mult_40_2 (operation)
			 a_21	 reset_loop/algorithm_loop/sub_40/minus_40 (operation)
 s_2_2	 c3	 s_2_3	 a_2	 reset_loop/algorithm_loop/c_40 (read)
			 a_6	 reset_loop/algorithm_loop/y_40 (write)
			 a_9	 reset_loop/algorithm_loop/add_40/plus_40 (operation)
			 a_12	 reset_loop/algorithm_loop/add_40/plus_40_2 (operation)
 s_2_3	 c4	 s_2_2	 a_0	 reset_loop/algorithm_loop/a_40 (read)
			 a_1	 reset_loop/algorithm_loop/b_40 (read)
			 a_3	 reset_loop/algorithm_loop/d_40 (read)
			 a_4	 reset_loop/algorithm_loop/e_40 (read)
			 a_5	 reset_loop/algorithm_loop/f_40 (read)
			 a_15	 reset_loop/algorithm_loop/mul_40/mult_40 (operation)
			 a_18	 reset_loop/algorithm_loop/mul_40/mult_40_2 (operation)
			 a_21	 reset_loop/algorithm_loop/sub_40/minus_40 (operation)
 +++++	 c5	 s_0_0	 a_7	 reset_loop/y_32 (write)
---------------------------------------------------------------------------
       ***********      Branch Conditions      ***********
---------------------------------------------------------------------------
 state	 condition	 source
---------------------------------------------------------------------------
c1        	true
c2        	true
c3        	true
c4        	true
c5        	true
---------------------------------------------------------------------------
===========================================================================
