Due: 12/09/03 (Presentation) 12/16/03 (Report)
The goal of the final project is to research an interesting problem related to network processors and the IXP1200. You are expected to come up with an original solution to one of the final project problems (based on the suggestions below), discuss it, and provide simulation and/or experimentation results. Altogether, the resulting report should be similar in style and quality of a tech report or a short conference paper.
There are two parts to the final project grade: 1/3 of the grade comes from the final project presentation on 12/9/03 (15 minutes + Q&A) and 2/3 of the grade comes from the final report that is due 12/16/03. Please note that this requires that you have most of your results completed by 12/9/03. The presentation will be graded in similar fashion as in-class presentations. The final report will be graded on presenting an adequate solution to the problem (40%), simulation or experimentation results to support solution (30%), and overall quality of writing, discussion of related work, etc. (30%).
Please choose one of the following topics. If you wish, you can propose a different project idea. Please see me about this by 11/26.
The topics are intentionally defined in broad terms to leave some room for your creativity. Fell free to come by my office and discuss your project with me at any time.
Project A: Implementation of Traffic Filter on the IXP1200
This project aims at implementing a simple traffic filter on the IXP1200 hardware. The IXP1200 should be set up to act as “bump-in-the-wire” (see Chapter 26). Each packet is inspected and classified as described below. For each class of traffic, it should be possible to specify if traffic is allowed to pass or not. The IXP1200 should forward or drop the packets accordingly.
The minimum types of traffic that should be supported are:
The project should discuss how such a traffic filter can be implemented most efficiently. It should be discussed in detail where (microblock or core) each component should reside. The performance of the implementation should be measured in simulation and on the hardware.
Project B: Analysis of Memory Contention on the IXP1200
This project aims at investigating the impact of memory contention on the IXP1200 performance. If the memory load increases, the memory access latency increases from the point of view of a thread. In this project, the memory should be modeled as a queuing system. The latency (or service time) should be derived analytically as a function of the request rate.
Then the model should be verified through simulation on the IXP1200 simulator. An application should be written for the microengines that generates memory requests with different rates that can be specified. Using the simulator, the memory access latency should be measured and compared to the analytic result.
Project C: Analysis IPv4 Packet Forwarding Processing on the IXP1200
This project aims at understanding the processing steps of IPv4 forwarding and how much processing each requires. Using the IXP1200 simulator and the Intel implementation of IPv4 forwarding, the various processing steps in the code should be identified (e.g., “packet gets read from buffer,” “destination address lookup,” etc.). For each step, the processing time should be derived (e.g., number of instructions executed, number of cycles stalled due to memory accesses, etc.). By varying the number of threads and the number of miroengines, the performance impact should be explored. For example, using a single thread will never cause queuing delay on memory accesses but it causes stalls. Many threads cause queuing delay but no stalls. What is the best configuration?
The final project report should include a concise problem statement, a discussion of the proposed solution, simulation and measurement results, related work etc. Altogether, the report should be around 10 pages including illustrations and graphs.
©2003 by Tilman Wolf