|
Introduction
to the Adaptive Viterbi Algorithm
Contact: Russell
Tessier (tessier@ecs.umass.edu)
Adaptive Viterbi
Algorithm
A discussion of the
development of a hardware implementation of the adaptive Viterbi algorithm
is provided in:
[1] S. Swaminathan,
R. Tessier, D. Goeckel, and W. Burleson "A
Dynamically-Reconfigurable Adaptive Viterbi Decoder FPGAs," ACM/SIGDA Symposium on Field Programmable Gate
Arrays, Monterey, CA, February 2002.
Additional
information is provided in:
[2] R. Tessier, S. Swaminathan, R. Ramaswamy, D.
Goeckel, and W. Burleson, A Reconfigurable, Power-Efficient
Adaptive Viterbi Decoder, in IEEE Transactions
on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488.
Hardware
Implementation
A zip file containing
RTL code which implements an AVA decoder is available here.
Two VHDL files are included. File cpe0lce.chd contains entity information
which allows the decoder to interface to the outside. Currently the
input/output interface is structured as a FIFO read/write interface. File
cpe0lca.vhd contains the decoder. The description of the hardware decoder
is included in comments in the VHDL files. Parameters for Nmax, T (called
initialT), and K are located at the beginning of cpe0lca.vhd. The RTL code
can be scaled by modifying these parameters based on the results in
Swaminathan's FPGA'02 paper. Unfortunately, the code as currently written
also requires a modification to a few processes if Nmax is changed.
Processes min1_update through min5_update determine the minimum path metric
among the surviving paths. Each process reduces the search space by about
half until only 2 possible choices are left (in min5_update). The number
and size of the processes require modification if Nmax is modified.
Additionally, if K is varied the bitwise XOR operations used to generate
"encoder_bit2_out0" and "encoder_bit2_out1" must be
changed manually. This design will compile without errors using Quartus II
version 5.1 using the project file located in the associated zip file.
|