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Introduction
to the ASOVA turbo decoder
This decoder can be
used to reduce the complexity of turbo decoding while maintaining a fixed
bit error rate.
Contact: Russell Tessier
(tessier@ecs.umass.edu)
ASOVA
Algorithm
A description of the
development of a hardware implementation of the ASOVA algorithm is provided
in:
[1] J. Liang, R.
Tessier, and D. Goeckel. "A
Dynamically-Reconfigurable, Power-Efficient Turbo Decoder," IEEE
Symposium on Field Programmable Custom Computing Machines, Napa, CA, April
2004.
[2] J. Liang. "Development and
Verification of System-on-a-Chip Communication Architecture," Ph.
D thesis, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, May 2004.
Hardware
Implementation
A zip file containing
RTL code which implements an ASOVA decoder is available here. Note that only the decoder is
included. The top level Verilog file is turboSram.v. Note that this HDL
code was designed to accept input and output from a dual-ported SRAM which
was shared with a NIOS processor. The NIOS processor has not been included
with this code. Several Verilog files are included. The files can be
compiled using the turboSram project file for Quartus II version 5.1. Note
that the list of Verilog files used in the design can be examined under the
"Project" menu item in Quartus II. Parameters for generator
polynomials (G1, G2), Nmax, T (called THRESHOLD_BASE), and various other
parameters are located in parameters.v
Scaling the Design
The default ASOVA
design in the zip file is for N_MAX = 4. Larger ASOVA decoders can be
created by modifying the N_MAX and NMAX_WIDTH parameters in parameters.v.
N_MAX should be a power of 2 and NMAX_WIDTH should be log2(N_MAX). Note
that the testbench has only been verified for N_MAX = 4.
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