This is the list of proposed projects for this class. Please check this site frequently as the projects get updated and new projects may be added. Students who will decide to take a project, will be required to submit the following reports:

• A short (1-2 page) preliminary project report, briefly summarizing the project idea and the proposed method to handle it - due February 28;
• Intermediate (midterm) project report (4-6 pages), summarizing the approach taken to solve it, and initial results - due March 28; and
• Final report, describing details of the taken approach, results, etc. - due April 26. Example of the final report will be posted soon.

Project 1 : Divider Circuit Generator

The goal of this project is to create software program that will automatically generate a divider circuit in verilog HDL. Follow the following steps.

• Read the following paper on Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism to understand what array divider circuit is, how it works, and what types of dividers exist (non-restoring and restoring).

• Understand the algorithm implemented by these two types of dividers. Perform at least one division step-by-step, by hand, of each.

• Illustrate the difference between non-restoring and restoring array dividers.

• Write a C++ code to generate an arbitrary non-restoring or restoring divider.
  • The input to the program is an integer number, n, representing the bit-width of the divisor operand (by default, the divider has 2n-1 bits).
  • The output of the program is a verilog netlist. The verilog file must be readable by the ABC tool (available from the class website).

1) You will need to develop and test your program on Ubuntu machine running Linux. Make sure it can be compiled on another Ubuntu machine.

2) To test your program, you should use ABC tool. Specifically, you will need to read the verilog file and simulate it on a sufficient number of test vectors to check if it works correctly.

3) When you submit your program, you must package all the files including the makefile . To learn about Makefile, consult the following link: Makefile tutorial .

This research project is related to a novel diagnosis and logic debugging method for gate-level arithmetic circuits. We have recently developed a method to detect logic bugs in a synthesized circuit that is caused by using a wrong gate ("gate replacement" error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic "signature". The location and type of the bug is determined by comparing signatures computed in both directions, using forward (PI to PO) and backward (PO to PI) rewriting. Once the error location is identified (at the place when the two signatures differ), the method is able to automatically correct the detected bug. The problem we are facing now is how to find at which point to compare the two signature, as this will indicate the location of the actual bug.

This idea of arithmetic debugging is illustrated in the following poster: poster-debugging.pdf
A more detailed description of the technique is given in the following paper: debugging-paper-ISVLSI-2015.pdf

The goal of the project is to come up with the strategy and an algorithm to guide the rewriting process to efficiently localize the error. You will have access to the rewriting software and all the tools needed to traverse the circuit. Your task is to write a higher level program in C, C++ or Python, that will try to localize the error in the most efficient way.

Generate a gate-level BLIF netlist of an arithmetic circuit, with the function provided by the user. Description of the BLIF format can be found on the class website in the tools menu under ABC.

• Input: 1) bit-width (integer) of the circuit operands; 2) the input signature, a polynomial describing the arithmetic function to be implemented by the circuit; for example: F = A*B + C is a multiply accumulate, where each operand is n-bit wide.
• Output: BLIF netlist of the circuit.

Arithmetic designs include Adders, Multipliers, Multiply-Accumulator, and similar circuits. The goal is to verify that an arithmetic circuit implemented in FPGA technology satisfies the specification provided by the verilog RTL description. We have all the necessary tools to perform this verification and your goal will be to run some experiments to evaluate their efficiency.
The following paper, Verification of Gate-level Arithmetic Circuits by Function Extraction, published at Design Automation Conference (DAC), June 2015, explains the main idea for gate-level ASIC designs. Now we want to test it for FPGAs. Practical knowledge of C/C++ programming is required.
Here are the specic tasks:
• Understand the basic idea of Computer algebraic verification method described in the paper.
• Learn the FPGA synthesis tool, Xilinx ISE and Altera Quartus. Understand how to use these tools to synthesize the designs with different metrics (such like, low power, high-performance, keep original structure, etc.).
• Synthesize the arithmetic designs (verilog files will be provided) using different metrics (area, delay, power, etc.).
• Use the tool presented in the DAC-2015 paper to verify the provided arithmetic designs synthesized to FPGA.

Good luck !