Synopsys^TM

Power Compiler

Use sold for official help

Power Compiler Design flow:

Power Compiler design flow (from Synopsys^TM)

Warning1: In order to use the following script, you have to setup Synopsys PLI interface first. PLI interface will enable you to read and write SAIF files during hdl simulation.For simplicity,I will setup PLI interface, the only thing what you need do is to use verilog_power command instead of verilog command when do verilog simulation based power estimation.

A simple example:16bit multipiler,I wrote three script files for it. This example is designed to introduce you to familiar with the Synopsys^TM Power Compiler.

1. Download this design mult16.v to your account.

2. Download testbench stim.v to your account.

3. Download three script files to your account

a.pc1.scr

b.pc2.scr

c. run

4. Run the following command

example> run

Warning2: Sucessful running requires target library;here I use typical.db from TSMC, put typical.db in your work directory, or reconfigure compile.scr

4. If everything work right,there should be four files generated in your directory :

Forward SAIF file from design : forward.saif

Back SAIF file from simulation: backward.saif

Rough time estimation for this power analysis: time.txt

Power report: power.txt