/******************************************************************
File: POW_EST.SCR
Date: Feb 05, 2002
Ning Weng

This script is used to generate the Forward SAIF file, which is 
the first step in this RTL power estimation flow. The output
SAIF file is written to <FORWARD SAIF FILE> 
******************************************************************/

/* configure your technology library */

sh "rm time.txt"
sh echo "start power estimation" >time.txt
sh date >>time.txt


power_preserve_rtl_hier_names = true 

link_library = typical.db
target_library = typical.db

sh "rm -r work"
sh "mkdir work"

define_design_lib work -path work

/* configure your DUT, should including all the design from lower level to higher 
one */

analyze -format verilog -lib work mult16.v 

echo "elaborating... be patient"

/* configure your highest DUT*/
elaborate mult16

link

/* configure your intermediate file,should be same with in your testbench*/

sh "rm forward.saif"

rtl2saif -output forward.saif -design mult16

/* configure your testbench name. Have to put PLI in your testbench */

sh "rm backward.saif"

sh "verilog_power mult16.v stim.v"

quit