State of the art microprocessors have one or more levels of on-chip caches. The trend is to increase the cache memory with the increasing transistor budget, because off-chip accesses are atleast an order of magnitude slower. By confining memory accesses on-chip, single cycle memory access latency can be achieved using Static RAMs. There is the added advantage of reducing power because driving signals through high capacitance I/O pads is less frequent. An examination of the die photos of high-end microprocessors show that anywhere from 15% to 40% of the die area is dedicated to on-chip caches.[1]

This tool for Energy dissipation in Caches is based on the paper," Analytical Energy Dissipation Models for Low Power Caches", by Milind B. Kamble and Kanad Ghose[1].Summary

This link summarizes the goals of this project


The following tools have been provided for obtaining the Energy dissipated in the cache. The tools are designed for a set-associative cache and hence can also be utilized for the direct mapped cache and the fully associative cache as they are special cases of the set associative cache.

1) Tool for determining Energy dissipation: This tool allows the user to enter various values inputs and computes the individual energy dissipation elements as well as the total energy dissipated. A graphical representation is also provided to show the ratio of the various energy dissipations.

Tools for comparing Energy dissipation for varying values of
2)Supply Voltage
3)Cache Associativity
4)Cache size
5)Line size.


1) Kamble,M.B and Ghose,K., "Analytical Energy Dissipation Models of Low Power Caches", in Proc. 1997, Int'l Symposium on low power electronics and design, Aug 1997,pp 143-148.
2) Energy efficiency of VLSI Caches: A comparative Study:- Kamble, Ghose-1997.
3) Modeling Energy Dissipation in Low Power Caches(1998) Milind B.Kamble, Kanad Ghose.
4) The tool used for displaying the results in graphical format is Javascript Graph Builder