This tool for Energy dissipation in Caches is based on the paper," Analytical Energy Dissipation Models for Low Power Caches", by Milind B. Kamble and Kanad Ghose.To accurately estimate cache power, the authors have developed a model for the static RAM cell and identified its main energy dissipating components. An energy dissipation model for set associative caches was then developed based on SRAM cells. The model developed was then validated by comparing it with the power estimated using a detailed simulator called CAPE ( Caache Power Estimator). The analytical models for conventional caches were found to be accurate to within 2% error.
The paper provides a detailed explanation of the various factors involved and the equations used in determining the energy dissipated in the cache. This tool uses the equations and is aimed at allowing the user to understand the effects of varying the various parameters involved, such as Supply voltage, the width of the address bus, cache block size etc.
The major components of the CMOS SRAM that dissipate energy in the cache are
1) Energy dissipated in the bit lines: Bit line dissipations are caused due to precharging in preparation for access and also during the actual read and write of the SRAM cells
2) Energy dissipated in the word lines: Word line dissipations are caused due to assertion of the word select line by the word line drivers to perform the read or write to the SRAM cells in the cache.
3) Energy dissipated in the output lines: Dissipation in the output lines are caused due to driving signals on the interconnects external to the cache
4) Energy dissipated in the address input lines: Input line dissipations are caused due to transitions on the input lines and input latches.
Energy dissipations that occur in the sense amplifiers, tag comparator, cache control logic and address comparators in write back mode are relatively much smaller and hence have been ignored in the calculations.