Sandip Kundu

I am a professor in the Department of Electrical and Computer Engineering at the University of Massachusetts Amherst.

Publications

Books, Book Chapters

Md. Nazmul Islam and Sandip Kundu, Chapter on IoT Security, Privacy and Trust in Sharing Economy via Blockchain, in Blockchain Cyber security, Trust, and Privacy Edited by Dr. Kim Kwang Raymond Choo, Dr. Ali Dehghantanha, and Dr. Reza M. Parizi, Springer Publications, In Press
Sandip Kundu and Aswin Sreedhar, Nanoscale CMOS VLSI Circuits: Design for Manufacturability, ISBN: 978-0071635196, McGraw-Hill Professional, 2010
Sandip Kundu and Alodeep Sanyal, Introduction Chapter in Power-Aware Testing and Test Strategies for Low Power Devices, Edited by Patrick Girard, Nicola Nicolici, Xiaoqing Wen, ISBN:978-1-4419-0927-5, Springer, 2009
Omer Khan, Sandip Kundu, Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines,, Book Series Lecture Notes in Computer Science, Springer, ISSN 0302-9743, ISBN 978-3-540-92989-5, 2009
Niraj Jha and Sandip Kundu, Testing and Reliable Design of CMOS Circuits, ISBN 0-7923-9056-3, TK7871.99.M44J49, Kluwer Academic Publishers, Boston, MA, 1990
Sudhakar Reddy and Sandip Kundu, Fault Detection and Design for Testability of CMOS Logic Circuits, Chapter in Testing and Diagnosis of VLSI and ULSI Edited by F. Lombardi and M. G. Sami(Eds), pp. 69-92, Kluwer Academic Publishers, Boston, MA, 1988

Patents

Weight compression/decompression system (US Patent No. 7197721)
Generalized fault model for defects and circuit marginalities (US Patent No. 7036063)
Method and apparatus for modeling and circuits with asynchronous behavior (US Patent No. 6,973,422)
Scan design for double-edge-triggered flip-flops (US Patent No. 6,938,225)
Method and apparatus for power supply noise modeling and test pattern development (US Patent No. 6,912,701)
System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation (US Patent No. 6,715,091)
Constrained signature-based test (US Patent No. 6,510,398)
Technique for sorting high frequency integrated circuits (US Patent No. 5,796,751)
System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle (US Patent No. 5,793,777)
CMOS transistor network to gate level model extractor for simulation, verification and test generation (US Patent No. 5,629,858)
Adjustable weighted random test pattern generator for logic circuits (US Patent No. 5,297,151)
A DFT technique for avoiding contention/conflict in logic built-in self-test (US Patent No. 7,096,397)

Journals

B. F. Goldstein, V. C. Patil, V. C. Ferreira, A. S. Nery, F. M. G. França and S. Kundu, Preventing DNN Model IP Theft via Hardware Obfuscation, in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 2, pp. 267-277, June 2021, doi: 10.1109/JETCAS.2021.3076151.
T. A. O. Alves, L. A. J. Marzulo, S. Kundu and F. M. G. França, Concurrency Analysis in Dynamic Dataflow Graphs, in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 1, pp. 44-54, 1 Jan.-March 2021, doi: 10.1109/TETC.2018.2799078.
Leandro Santiago de Araùjo, Leticia Dias Verona, Fábio Medeiros Rangel, Fabricio Firmino de Faria, Daniel Sadoc Menasche, Wouter Caarls, Mauricio Breternitz, Sandip Kundu, Priscila Machado Vieira Lima, Felipe Maia Galvão França, Memory Efficient Weightless Neural Network using Bloom Filter, Neurocomputing, February 2020, 10.1016/j.neucom.2020.01.
Pascal Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad Khellah, James Tschanz and Vivek De, Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10nm CMOS, IEEE Solid-State Circuits Letters, Volume: 2, Issue: 9, Sept. 2019
Md. Nazmul Islam, Sandip Kundu, Enabling IC Traceability via Blockchain Pegged to Embedded PUF, ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM Transactions on Design Automation of Electronic Systems, Vol 24, 3, Article 36 (April 2019), 23 pages. DOI: https://doi.org/10.1145/
Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu, Design of Robust, High Entropy Strong PUFs via Weightless Neural Network, Journal of Hardware and Systems Security, September 2019, Volume 3, Issue 3
Tiago Alves, Leandro A. J. Marzulo, Felipe M. G. França and Sandip Kundu, Concurrency Analysis in Dynamic Dataflow Graphs, IEEE Transactions on Emerging Topics in Computing, (preprint: https://www.computer.org/csdl/journal/ec/5555/01/08269827/13rRUwjoNBc)
Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu, On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging, IEEE Trans. on Circuits and Systems 65-I (3): 960- (2017)
Vijayakumar, Arunkumar, Vinay C. Patil, and Sandip Kundu. On Improving Reliability of SRAM-Based Physically Unclonable Functions, Journal of Low Power Electronics and Applications 7, (2017): 2, http://www.mdpi.com/2079-9268/7/1/2/htm
Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, and Sandip Kundu, Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques, IEEE Transactions on Information Forensics and Security, vol. 12, no. 1, pp. 64-77, Jan. 2017.
Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li and Sandip Kundu, Abstraction-Guided Simulation Using Markov Analysis for Functional Verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 2, pp. 285-297, Feb. 2016
Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kundu. Exploring Heterogeneity within a Core for Improved Power Efficiency, IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 4, pp. 1057-1069, April 2016
Vikram B. Suresh, Sandip Kundu, Managing Test Coverage Uncertainty due to Random Noise in nano-CMOS: A Case-Study on an SRAM Array, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no.1, pp.155-165, Jan. 2016
R.Rodrigues, I.Koren and S.Kundu, Does the Sharing of Execution Units Improve Performance/Power of Multicores?, ACM Transactions on Embedded Computing Systems (TECS), Volume 14, Issue 1, Article No. 17, January 2015
Abhisek Pan, Rance Rodrigues and Sandip Kundu, A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors, ACM Transactions on Embedded Computing Systems (TECS), Volume 14, Issue 1, Article No. 12, January 2015
Kunal Ganeshpure and Sandip Kundu, Performance-driven dynamic thermal management of MPSoC based on task rescheduling, ACM Trans. Des. Autom. Electron. Syst. 19, 2, Article 11 (March 2014), 33 pages.
Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel, Globally Constrained Locally Optimized 3D Power Delivery Networks, IEEE Transactions on VLSI Systems, vol.22, no.10, pp.2131-2144, Oct. 2014
R. Rodrigues, A. Annamalai, and S. Kundu. A Low Power Instruction Replay Mechanism for Design of Resilient Microprocessors. ACM Transactions on Embedded Computing Systems (TECS) Article 85, 23 pages, March 2014
R.Rodrigues, A.Annamalai, I.Koren and S.Kundu, A Study on the use of Performance Counters to Estimate Power in Microprocessors, IEEE Transactions on Circuit and Systems II: Express Briefs, vol.60, no.12, pp. 882-886, Dec. 2013
Kunal Ganeshpure and Sandip Kundu, Game theoretic Approach for Run-time Task Scheduling on an MPSoC, IET Circuits, Devices and Systems 7.5 (2013): 243-252.
A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo, A. Virazel, A Study of Tapered 3D TSVs for Power and Thermal Integrity, IEEE Transactions on VLSI, Feb. 2013, pp. 306-319
Rance Rodrigues, Arunachalam Annamalai, Israel Koren, and Sandip Kundu, Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing, ACM Transactions on Design Automation of Electronic Systems, Vol. 18, No. 1, pp. 5:1-5:23, January 2013
Alodeep Sanyal, Kunal Ganeshpure, Sandip Kundu, Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading from Fanout Nodes in Presence of Gate Delays, IEEE Transactions on VLSI, vol. 20, number 3, 2012, pp. 424-436
Aswin Sreedhar, Sandip Kundu and Israel Koren, On Reliability Trojan Injection and Detection, Journal of Low Power Electronics, vol 8, number 5, 2012, pp. 674-683
Omer Khan and Sandip Kundu, An Empirical Model for Cooperative Resizing of Processor Structures to Exploit Power-Performance Efficiency at Runtime, Journal of IET Circuits, Devices and Systems, September 2012, pp. 355 - 365
Sudarshan Srinivasan, Kunal P Ganeshpure, Sandip Kundu, A Wavelet based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip, Vol. 31, No. 12, pp. 1867-1880, December 2012
Kunal Ganeshpure, Alodeep Sanyal and Sandip Kundu, A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays, IEEE Transactions on Computers, vol. 61, no. 7, pp. 986-998, July 2012
Michael Buttrick, Sandip Kundu, On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs, Journal of Electronic Testing, vol. 28, pp: 93-101, Feb 2012
Omer Khan and Sandip Kundu, Hardware/Software Co-design Architecture for Online Testing in Chip Multiprocessors, IEEE Transactions on Dependable and Secure Computing, pp. 714-727, September/October, 2011.
Omer Khan and Sandip Kundu, Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors, Transactions on High-Performance Embedded Architectures and Compilers, Volume 4, LNCS 6760, pp. 84-110, 2011
Alodeep Sanyal, Syed M. Alam and Sandip Kundu, Built-In Self-Test for Detection and Characterization of Transient and Parametric Failures, IEEE Design and Test, vol 27, number 5, 2010, Pages 50-
Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey, Test Pattern Generation for Droop Faults, IET Comput. Digit. Tech, vol 4, 2010, Pages 274-284
Omer Khan, Sandip Kundu, Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors, IEEE Transactions on Computers, pp. 651-665, May, 2010.
Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu. An Efficient Technique for Leakage Current Estimation in Nano-Scaled CMOS Circuits Incorporating Self-loading Effects, IEEE Transactions on Computers, vol 59, number 7, 2010, Pages 922-932
Kunal P. Ganeshpure and Sandip Kundu, On ATPG for Multiple Aggressor Crosstalk Faults, IEEE Transactions on CAD, vol. 29, pp. 774-787, May 2010
Hyunbean Yi, Sungju Park, and Sandip Kundu, On-Chip Support for NoC-based SoC Debugging, IEEE Transactions on Circuits and Systems I, vol 57, number 7, 2010, Pages 1608-1617
Hyunbean Yi, Sandip Kundu, S. Cho and S. Park, A Scan Cell Design for Scan-based Debugging of an SoC with Multiple Clock Domains, IEEE Transactions on Circuits and Systems II, vol 57, No 7, 2010, Pages 561-565
R. A. Shafik, B. M. Al-Hashimi, S. Kundu, A. Ejlali, Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific MPSoC, Journal of Low Power Electronics, August 2009
Alodeep Sanyal, Kunal Ganeshpure, Sandip Kundu, An Improved Soft Error Rate Measurement Technique, IEEE Trans. on CAD, pp. 596-600, April 2009
Aswin Sreedhar, Sandip Kundu, Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays, Journal of Low Power Electronics, 4, 392-401 (2008)
Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu, On Composite Leakage Current Maximization, Journal of Electronic Testing: Theory and Applications (JETTA), pp. 405-420, Volume 24, Number 4, August, 2008
Piet Engelke, Ilia Polian. Michel Renovell, Sandip Kundu, Bernd Becker, Bharath Seshadri, and Irith Pomeranz, On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing, IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008)
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker, Power Droop Testing, IEEE Design and Test of Computers, vol. 24, no. 3, pp. 276-284, May-June, 2007
Sandip Kundu, Aswin Sreedhar, Alodeep Sanyal, Forbidden pitches in Sub-Wavelength Lithography and their Implications on Design, The Journal of Computer-Aided Materials Design, ISSN: 0928-1045, Vol. 14, No 1, 2007, pp. 79-89
Sandip Kundu, Sujit Zachariah, Yi-Shing Chang, Chandra Tirumurti, On modeling interconnect cross-talk faults, IEEE Transactions on CAD, vol. 24 , no. 12, Dec. 2005, pp. 1909 - 1915
Irith Pomeranz, Sudhakar M. Reddy and Sandip Kundu, On the Characterization and Efficient Computation of Hard-to-Detect Bridging Faults, IEEE Transactions on CAD, vol. 23, no. 12, December 2004
Sandip Kundu, Pitfalls of Hierarchical Fault Simulation, IEEE Transactions on CAD, February 2004, pp. 312- 314
Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy, Masking of Unknown Output Values During Output Response Compression by Using Comparison Units, IEEE Transactions on Computers, vol. 53, Jan. 2004, pp. 83 - 89
Sandip Kundu, Sujit Zachariah, Sanjay Sengupta and Rajesh Galivanche, Test Challenges in Nanometer Technologies, Journal of Electronic Testing: Theory and Applications, pp. 209-218, 2001
Sanjay Sengupta, Sandip Kundu, Sreejit Chakravarty, Praveen Parvathala, Rajesh Galivanche, George Kosonocky, Mike Rodgers, and TM Mak, Defect-Based Test: A Key Enabler for Successful Migration to Structural Test, Intel Technical Journal, 1999 1st quarterly issue
Sandip Kundu, E. S. Sogomonyan and M. Goessel, Self-checking comparator with one periodic output, IEEE Transactions on Computers, vol. 45, no. 3, March 1996
Sandip Kundu, On construction of non-systematic t-symmetric error correcting/ all unidirectional error detecting codes, IEICE Transactions on Inf. System, vol. E78-D, No. 5, May 1995
Sandip Kundu, An incremental algorithm for identification of longest (shortest) paths, Integration, pp. 25-31, vol. 17, 1994
Sandip Kundu, An efficient technique for obtaining unate implementation of functions through input encoding, Integration, pp. 265-270, vol. 17, 1994
Leendert Huisman and Sandip Kundu, Highly reliable symmetric networks, IEEE Trans. on Parallel and Distributed Processing, pp. 94-97, Jan 1994
Sandip Kundu, Diagnosing Scan Chain Faults, IEEE Transactions on VLSI Systems, pp. 512-516, vol. 2, No. 4, December 1994
Sandip Kundu, Sudhakar M. Reddy and Niraj Jha, On The Design of Robustly Testable CMOS Combinational Logic Circuits IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 1036-1048, August 1991
Sandip Kundu and Sudhakar M. Reddy, A practical design of embedded TSC checkers, IEEE Design and Test, pp. 5-12, August 1990
Sandip Kundu and Sudhakar M. Reddy, Robust Tests for Parity Trees, Journal of Electronic Testing: Theory and applications, pp. 191-200, August 1990
Sandip Kundu and Sudhakar M. Reddy, On symmetric error correcting and all unidirectional error detecting codes, IEEE Trans. on Computers, Vol C-39, pp. 752 - 761, June 1990
Sandip Kundu, Design of Multi-output CMOS Combinational Logic Circuits for Robust Testability, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 1222-1226, November 1989

Refereed Conferences and Workshops

Jonathan Ponader, Kyle Thomas, Sandip Kundu, Yan Solihin, MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs, the 51st IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2021)
Brunno F Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago, Victor C. Ferreira, Alexandre S. Nery, Sandip Kundu and Felipe França, A Lightweight Error-Resiliency Mechanism for Deep Neural Networks, 22\textsuperscript{nd} International Symposium on Quality Electronic Design (ISQED’21), April 4-7, 2021
Vinay Patil, Sandip Kundu, On Leveraging Multi-threshold FinFETs for Design Obfuscation, IEEE Computer Society Annual Symposium on VLSI, Limassol, Cyprus, July 6-8, 2020
Irith Pomeranz, Sandip Kundu Reduced Fault Coverage as a Target for Design Scaffolding Security, 26th IEEE International Symposium on On-Line Testing and Robust System Design, Naples, Italy, July 13-15, 2020
Leandro Santiago de Araùjo, Leandro Augusto Justen Marzulo, Tiago Assumpção de Oliveira Alves, Felipe Maia Galvãoo França, Israel Koren and Sandip Kundu, Building a Portable Deeply-Nested Implicit Information Flow Tracking, ACM International Conference on Computing Frontiers, Catania, Sicily, Italy, May 11 - May 13, 2020
Tiago Alves, Sandip Kundu, Towards Adversarial Attack Resistant Deep Neural Networks, European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, Bruges, Belgium, October 2-4, 2020
Brunno F Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago, Victor C. Ferreira, Alexandre S. Nery, Sandip Kundu and Felipe M. G. França, Reliability Evaluation of Compressed Deep Learning Models, 11th IEEE Latin American Symposium on Circuits and Systems, San Josè, Costa Rica, February 25-28, 2020
Leandro Santiago de Araùjo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu, Efficient Testing of Physically Unclonable Functions for Uniqueness, IEEE 28thAsian Test Symposium (ATS), December 2019
Pascal Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad Khellah, James Tschanz and Vivek De, Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10nm CMOS, 45thEuropean Solid-State Circuits Conference, Krakow, Poland, September 23-26, 2019
Leandro Santiago de Araùjo, Victor Cruz Ferreira, Brunno Figueroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu and Felipe M. G. França, Hardware-Accelerated Similarity Search with Multi-Index Hashing, 17thIEEE International Conference on Pervasive Intelligence and Computing (PICom 2019), August 5-8 2019, Fukuoka, Japan
Md Nazmul Islam, Sandip Kundu, Remote Configuration of Integrated Circuit Features and Firmware Management via Smart Contract, IEEE International Conference on Blockchain, Atlanta, July 14 - July 17, 2019
Tiago Alves, Felipe M.G. França and Sandip Kundu, MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems, In Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 411-415. ACM, 2019
Leandro Santiago de Araùjoet. al., Memory Efficient Weightless Neural Network using Bloom Filter,27thEuropean Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, Bruges, Belgium, 24 - 26 April 2019
Horácio L.França, Charles B. Prado, Vinay C. Patil, and Sandip Kundu, Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs, In 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 25-30, IEEE, 2018
13.Anderson Luiz Sartor, Arthur F. Lorenzon, Sandip Kundu, Israel Koren and Antonio Carlos S. Beck, Adaptive and Polymorphic VLIW Processor to Optimize Fault Tolerance, Energy Consumption, and Performance, ACM International Conference on Computing Frontiers, 2018 http://www.computingfrontiers.org/2018/, Best Paper Award
Md Nazmul Islam, Sandip Kundu, On IC Traceability via Blockchain, 23rd International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, April 16-19, 2018
A. Pouraghily, M. Islam, S. Kundu, T. Wolf, Privacy in Blockchain-Enabled IoT Devices, ACM/IEEE International Conference on Internet of Things Design and Implementation (IoTDI), April 17-20, 2018
Md Nazmul Islam, Sandip Kundu, Preserving IoT Privacy in Sharing Economy via Smart Contract, ACM/IEEE International Conference on Internet of Things Design and Implementation (IoTDI), April 17-20, 2018
Md Nazmul Islam, Sandip Kundu, PMU-Trojan: On Exploiting Power Management Side Channel for Information Leakage, 23rdAsia and South Pacific Design Automation Conference, 2018
Tiago Alves, Leandro A. J. Marzulo, Felipe M. G. França and Sandip Kundu, A Resilient Scheduler for Dataflow Execution, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2017
Leandro Santiago, Vinay C Patil, Sandip Kundu, Felipe M. G. Fraça, Charles B. Prado, Tiago A. O. Alves and Leandro A. J. Marzulo, Realizing Strong PUF from Weak PUF via Neural Computing, 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2017
Vinay C Patil, Arunkumar Vijayakumar and Sandip Kundu, Manufacturer turned Attacker: Dangers of Stealthy Trojans via Threshold Voltage Manipulation, 2017 IEEE 26thNorth Atlantic Test Workshop (NATW), Providence, RI, 2017
Pavithra Ramesh, Vinay C Patil and Sandip Kundu, Peer Pressure on Identity: On Requirements for Disambiguating PUFs in Noisy Environment, 2017 IEEE 26thNorth Atlantic Test Workshop (NATW), Providence, RI, 2017
Vinay C Patil, Arunkumar Vijayakumar, Daniel E. Holcomb and Sandip Kundu, Improving Reliability of Weak PUFs via Circuit Techniques to Enhance Mismatch, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2017
Md. Nazmul Islam, Vinay C Patil, Sandip Kundu, A Guide to Graceful Aging: How Not to Overindulge in Post-Silicon Burn-in for Enhancing Reliability of Weak PUF, ISCAS, 2017
Md. Nazmul Islam, Vinay C Patil, Sandip Kundu, Determining Proximal Geolocation of IoT Edge Devices via Covert Channel, ISQED, 2017
Md. Nazmul Islam, Sandip Kundu, An Analytical Model for Predicting the Residual Life of an IC and Design of Residual-Life Meter, VLSI Test Symposium, 2017
M. N. Islam and S. Kundu, Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations, 2016 IEEE 25th Asian Test Symposium (ATS), Hiroshima, Japan, 2016, pp. 240-245
S. Srinivasan, I. Koren and S. Kundu, Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification, 2016 IEEE 34th International Conference on Computer Design (ICCD), Scottsdale, AZ, 2016, pp. 528-535
V. C. Patil, A. Vijayakumar and S. Kundu, On meta-obfuscation of physical layouts to conceal design characteristics, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Storrs, CT, 2016, pp. 147-152.
M. N. Islam and S. Kundu, Modeling Residual Life of an IC Considering Multiple Aging Mechanisms, 2016 IEEE 25th North Atlantic Test Workshop (NATW), Providence, RI, 2016, pp. 24-27
A. Vijayakumar, V. C. Patil, C. B. Prado and S. Kundu, Machine learning resistant strong PUF: Possible or a pipe dream?, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, 2016, pp. 19-24
Vinay Patil, Arunkumar Vijayakumar and Sandip Kundu, Preventing Integrated Circuit Piracy via Custom Encoding of Hardware Instruction Set, 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016, pp. 234-241
Arunkumar Vijayakumar, Vinay Patil and Sandip Kundu, On Testing Physically Unclonable Functions for Uniqueness, 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016, pp. 368-373
Arunkumar Vijayakumar, Vinay Patil and Sandip Kundu, An Efficient Method for Clock Skew Scheduling to reduce Peak Current, 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 505-510
S. Srinivasan, N. Kurella, I. Koren and S. Kundu, Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors, 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 563-564
S. Kundu and O. Khan, Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores, 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 12-13
M. N. Islam and S. Kundu, Modeling Residual Life of an IC Considering Multiple Aging Mechanisms, IEEE 25th North Atlantic Test Workshop (NATW), RI, USA, 2016, pp. 24-27
Sudarshan Srinivasan, Israel Koren and Sandip Kundu, Online Mechanism for Reliability and Power-Efficiency Management of a Dynamically Reconfigurable Core, 33rd IEEE International Conference on Computer Design (ICCD), 2015 , New York, NY, 2015, pp. 327-334
Arunkumar Vijayakumar, Sandip Kundu, A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics, DATE 2015, pp. 653-658
Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu and Felipe M. G. França, Domino Effect Protection on Dataflow Error Detection and Recovery, DFTS 2014
Sudarshan Srinivasan, Nithesh Kurella, Rance Rodrigues, Sandip Kundu and Israel Koren, A Runtime Support Mechanism for Fast Mode Switching of a Self-Morphing Core for Power Efficiency, PACT 2014
Tiago Alves, Sandip Kundu, Leandro Marzulo, Felipe Franca, Online Error Detection/Recovery for Dataflow Execution, IOLTS 2014
Arunachalam Annamalai, Rance Rodrigues, Israel Koren and Sandip Kundu, Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores, ISVLSI 2014
Bharath Phanibhushana and Sandip Kundu, Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip, ISVLSI 2014
Arunkumar Vijayakumar and Sandip Kundu, Glitch Power Reduction via Clock Skew Scheduling, ISVLSI 2014
Arunkumar Vijayakumar, Vinay C Patil and Sandip Kundu, On maximizing decoupling capacitance of clock-gated logic for robust power delivery, ISVLSI 2014
Siva Nishok Dhanuskodi, Arunkumar Vijayakumar and Sandip Kundu, A Chaotic Ring Oscillator based Random Number Generator, HOST 2014
Arunkumar Vijayakumar, Vinay C Patil, Girish Paladugu, Sandip Kundu, On Pattern Generation for Maximizing IR Drop, ISQED 2014
Rance Rodrigues, Israel Koren and Sandip Kundu, Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core, 27th International Conference on VLSI Design, Mumbai, 2014
Raghavan Kumar, Siva Nishok Dhanuskodi and Sandip Kundu, On Manufacturing-Aware Physical Design to Improve Uniqueness of Silicon-Based Physically Unclonable Functions, 27th International Conference on VLSI Design, Mumbai, 2014
Rance Rodrigues and Sandip Kundu, A Low Power Architecture for Online Detection of Execution Errors in SMT Processors, 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Vikram Suresh, Sandip Kundu, Managing Test Coverage Uncertainty due to Thermal Noise in nano-CMOS: A Case Study on an SRAM Array, In. Conf. on Computer Design, 2013
Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren and Sandip Kundu, On Dynamic Polymorphing of a Superscalar Core for Improving Energy Efficiency, In. Conf. on Computer Design, 2013
Annamalai, R. Rodrigues, I. Koren, and S. Kundu, An Opportunistic Prediction-based Thread Scheduling to Maximize Throughput/Watt in AMPs. Submitted to International Conference on Parallel Architectures and Compilation Techniques (PACT), 2013.
Vikram Suresh and Sandip Kundu, On Analyzing and Mitigating SRAM BER due to Random Thermal Noise, IEEE Computer Society Annual Symposium on VLSI, 2013
Kunal Ganeshpure and Sandip Kundu, On Run-time Task Graph Extraction in MPSoC, IEEE Computer Society Annual Symposium on VLSI, 2013
Sudarshan Srinivasan, Raghavan Kumar and Sandip Kundu, Program Phase Duration Prediction and its Application to Fine-Grain Power Management, IEEE Computer Society Annual Symposium on VLSI, 2013
Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren and Sandip Kundu, A study on Polymorphing Superscalar Processor Dynamically to Improve Power Efficiency, IEEE Computer Society Annual Symposium on VLSI, 2013
A. Annamalai, R. Kumar, A. Vijayakumar, S. Kundu, A System-level Solution for Managing Spatial Temperature Gradients in Thinned 3D ICs, International Symposium on Quality Electronic Design (ISQED) 2013
Vinay C Patil, Sudarshan Srinivasan, Wayne P Burleson and Sandip Kundu, Impact of Clock-Gating on Power Distribution Network using Wavelet Analysis, VLSI Design Conference, Pune, India, 2013
Rance Rodrigues, Arunachalam Annamalai, Israel Koren and Sandip Kundu, Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency, 24th International Symposium on Computer Architecture and High Performance Computing (SBACPAD), 2012
Rance Rodrigues, Israel Koren and Sandip Kundu, A Mechanism to Verify Cache Coherence Transactions in Multicore Systems, International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Kunal Ganeshpure and Sandip Kundu, Reducing Temperature Variation in 3D Integrated Circuits using Heat Pipes, ISVLSI 2012
Kunal Ganeshpure and Sandip Kundu, A DFT Methodology for Repairing Embedded Memories of Large MPSoCs, ISVLSI 2012
Arunkumar Vijayakumar, Raghavan Kumar and Sandip Kundu, On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors, ISVLSI 2012
Raghavan Kumar, Vinay C Patil and Sandip Kundu, On Design of Temperature Invariant Physically Unclonable Functions based on Ring Oscillators, ISVLSI 2012
Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel, Electro-Thermal Analysis of 3D Power Delivery Networks, Design Automation Conference, 2012
Arunachalam Annamalai, Rance Rodrigues, Israel Koren and Sandip Kundu, Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt, HPPAC 2012
Sudarshan Srinivasan and Sandip Kundu, Functional Test Pattern Generation for Maximizing Temperature in 3D IC Chip Stack, ISQED, 2012
Vikram Suresh, Priyamvada Vijayakumar, Sandip Kundu, On Lithography Aware Metal-Fill Insertion, ISQED, 2012
Nishant Dhumane and Sandip Kundu, Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield, ISQED, 2012
Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu and Omer Khan, Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores, Parallel Architectures and Compilation Techniques (PACT), 2011
Rance Rodrigues and Sandip Kundu, An Online Mechanism to Verify Datapath Execution using Existing Resources in Chip Multiprocessors, Asian Test Symposium, 2011
Michael Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen and H.-J. Wunderlich, Efficient BDD-based Fault Simulation in Presence of Unknown Values, Asian Test Symposium, 2011
Vikram Suresh, Priyamvada Vijayakumar and Sandip Kundu, Lithography Aware Critical Area Estimation and Yield Analysis, International Test Conference, 2011
Bharath Phanibhushana, Kunal Ganeshpure and Sandip Kundu, Task Model for On-Chip Communication Infrastructure Design for Multicore Systems, International Conference on Computer Design, 2011
Rance Rodrigues, Sandip Kundu and Israel Koren, An Architecture to enable Life Cycle Testing in CMPs, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2011
Rance Rodrigues, Sandip Kundu, On Graceful Degradation of Chip Multiprocessors in Presence of Faults via Flexible Pooling of Critical Execution Units, Int. Online Test Symposium, 2011
Rance Rodrigues, Sandip Kundu, On Graceful Degradation of Chip Multiprocessors in Presence of Faults via Resource Banking, Int. Online Test Symposium, 2011
Nishant Dhumane, Sudheendra Srivathsa and Sandip Kundu, Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability, IEEE International Symposium on VLSI, 2011
Vikram Suresh, Priyamvada Vijayakumar and Sandip Kundu, On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements, IEEE International Symposium on VLSI, 2011
Raghavan Kumar, Vinay C Patil and Sandip Kundu , Design of Unique and Reliable Physically Unclonable Functions based on Current Starved Inverter Chain, IEEE International Symposium on VLSI, 2011
Michael Buttrick and Sandip Kundu, Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs, IEEE International Symposium on VLSI, 2011
Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty and Sandip Kundu, On Improving Reliability of Delay Based Physically Unclonable Functions under Temperature Variations, IEEE Int. Symposium on Hardware-Oriented Security and Trust, 2011
Sudarshan Srinivasan, Arunkumar Vijayakumar, Bharath Phanibhushana, Sandip Kundu, Stress Aware Switching Activity Driven Low Power Design of Critical Paths in Nanoscale CMOS Circuits, 21st ACM GLSVLSI Conference, 2011
Aswin Sreedhar and Sandip Kundu, On Discovery of “Missing” Physical Design Rules via Diagnosis of Soft-faults, ISQED, 2011
Rance Rodrigues and Sandip Kundu, Model Based Double Patterning Lithography (DPL) and Simulated Annealing (SA), ISQED, 2011
Sudarshan Srinivasan, Kunal P Ganeshpure, Sandip Kundu, Maximizing Hotspot Temperature: Wavelet based Modelling of Heating and Cooling Profile of Functional Workloads, ISQED, 2011
Michael Buttrick and Sandip Kundu, On Testing Prebond Dies with Incomplete Clock Networks in 3D ICs Using DLLs, Design Automation and Test in Europe, 2011
Aswin Sreedhar and Sandip Kundu, Physically Unclonable Functions for Embedded Security Using Lithographic Variation, Design Automation and Test in Europe, 2011
Aswin Sreedhar and Sandip Kundu, Modeling Manufacturing Process Variation for Design and Test, Design Automation and Test in Europe, 2011
Aswin Sreedhar and Sandip Kundu, On Design of Test Structures for Lithographic Process Corner Identification, Design Automation and Test in Europe, 2011
Michael Buttrick and Sandip Kundu, Low-Power DLL-based On-Product Clock Generation for 3D Integrated Circuit Testing, WRTLT, 2010
Shruti Vyas, Aswin Sreedhar and Sandip Kundu, DCT-based Scheme to Accelerate Multimedia Search in NAND Flash Memories, International SoC Design Conference, pp. 67-70, Nov, 2010
Bharath Phanibhushana, Priyamvada Vijayakumar, Prasad Shabadi, Gayatri Prabhu and Sandip Kundu, Towards Efficient On-chip Sensor Interconnect Architecture for Multi-core Processors, International SoC Design Conference, pp. 307-310, Nov, 2010
Sudheendra K. Srivathsa, Vikram B. Suresh, Pavan Panchapakeshan and Sandip Kundu, Dynamic Thermal Management for System-on-Chip using Bus Arbitration, International SoC Design Conference, pp. 372-375, Nov, 2010
Kunal Ganeshpure and Sandip Kundu, On Run Time Task Graph Extraction of SoC, International SoC Design Conference, pp. 380-383, Nov, 2010
S. Khursheed, S. Zhong, B. Al-Hashimi, R. Aitken, and S. Kundu, Modeling the Impact of Process Variation on Resistive Bridge Defects, International Test Conference, 2010
Anup Das, Rance Rodrigues, Israel Koren and Sandip Kundu, A Study on Performance Benefits of Core Morphing in a Asymmetric Multicore Processor, International Conference on Computer Design, 2010
Rance Rodrigues, Sandip Kundu, Shadow Checker: A Low-Cost Hardware Scheme for Online Detection of Faults in Small Memory Structures of a Microprocessor, International Test Conference, 2010
Lokesh Subramany, Rance Rodrigues and Sandip Kundu, Detecting Shorts And Open Faults In A Mask Using Lithography Simulation, 19th NATW, Hopewell Junction, NY, 2010
Rance Rodrigues, Sandip Kundu, A Mask Double Patterning Technique Using Litho Simulation By Wavelet Transform, 20th ACM GLSVLSI Conference, pp. 103-106, Providence, 2010
Omer Khan, Sandip Kundu, A Model to Exploit Power-Performance Efficiency in Superscalar Processors Via Structure Resizing, 20th ACM GLSVLSI Conference, pp. 215-220, Providence, 2010
Shruti Vyas, Aswin Sreedhar, Sandip Kundu, TURBONFS: Turbo Nand Flash Search, 20th ACM GLSVLSI Conference, pp. 251-256, Providence, 2010
Omer Khan, Sandip Kundu, A Self-Adaptive Scheduler for Asymmetric Multi-Cores, 20th ACM GLSVLSI Conference, pp. 397-400, Providence, 2010
Aswin Sreedhar and Sandip Kundu, EM calibration based on post-OPC layout synthesis, Design for Manufacturability through Design-Process Integration at SPIE Symposium on Advanced Lithography, February 2010, San Jose, CA
Aswin Sreedhar and Sandip Kundu, Stat-LRC: statistical rules check for variational lithography, Design for Manufacturability through Design-Process Integration at SPIE Symposium on Advanced Lithography, February 2010, San Jose, CA
Rance Rodrigues, Aswin Sreedhar and Sandip Kundu, Optical Lithography Simulation with Focus Variation using Wavelet Transform, VLSI Conference 2010
Hyunbean Yi, Kunal Ganeshpure, Shinjini Kundu, Sungju Park and Sandip Kundu, A System Maintenance Architecture via Ethernet, IEEE International Workshop on Reliability Aware System Design and Test, Bangalore 2010
Aswin Sreedhar and Sandip Kundu, Statistical Timing Analysis based on simulation of Lithographic process, ICCD 2009, October 2-4, Lake Tahoe CA
Rance Rodrigues, Aswin Sreedhar and Sandip Kundu, Optical Lithography Simulation using Wavelet Transform, at ICCD 2009, October 2-4, Lake Tahoe CA
Aarti Choudhary, Sandip Kundu, A Process Variation Tolerant Self-Compensating Sense Amplifier Design, IEEE Computer Society Annual Symposium on VLSI, Tampa, 2009
Spandana Remarsu, Sandip Kundu, On Process Variation Tolerant Low Cost Thermal Sensor Design in 32nm CMOS Technology, 19th ACM GLSVLSI Conference, Boston, 2009
Nagaraj Kelageri, Sandip Kundu, Process Variation Mitigation via Post Silicon Clock Tuning, 19th ACM GLSVLSI Conference, pp. 227-232, Boston, 2009
Alodeep Sanyal, Abhisek Pan, Sandip Kundu, A Study on Impact of Aggressor Derating in the Context of Multiple Crosstalk Effects in Integrated Circuits, 19th ACM GLSVLSI Conference, pp. 529-534, Boston, 2009
Kunal Ganeshpure, Ilia Polian, Bernd Becker, Sandip Kundu, Reducing Temperature Variability by Routing Heat Pipes, 19th ACM GLSVLSI Conference, pp. 63-68, Boston, 2009
Aarti Choudhary, Sandip Kundu, A Process Variation Tolerant Self-Compensating FinFET based Sense Amplifier Design, 19th ACM GLSVLSI Conference, Boston, 2009
Omer Khan, Sandip Kundu, A Self-Adaptive System Architecture to Address Transistor Aging, pp. 81-86, DATE 2009
Omer Khan, Sandip Kundu, Hardware/Software Co-design Architecture for Thermal Management of Chip Multiprocessors, pp. 952-957, DATE 2009
Abhisek Pan, Omer Khan, Sandip Kundu, Improving Yield and Reliability of Chip Multiprocessors, pp. 490-495, DATE 2009
Nagaraj Kelageri, Sandip Kundu, A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation, pp. 292-295, DATE 2009
Aswin Sreedhar, Sandip Kundu, On Linewidth-based Yield Analysis for Nanometer Lithography, pp. 381-386, DATE 2009 (Best Paper Award)
Kunal Ganeshpure, Sandip Kundu, An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays, VLSI 2009
Omer Khan and Sandip Kundu, Run-Time Reconfiguration for Performance and Power Optimizations in Heterogeneous Chip Multiprocessors, 3rd HiPEAC Workshop on Reconfigurable Computing, January 2009
Alodeep Sanyal, Abhisek Pan, Sandip Kundu, A Study on Impact of Loading Effect on Capacitive Crosstalk Noise, ISQED 2009
Omer Khan and Sandip Kundu, A Framework for Predictive Dynamic Temperature Management of Microprocessor Systems, IEEE/ACM 2008 Int’l Conference on Computer Aided Design, 2008
Omer Khan and Sandip Kundu, Automatic Adjustment of System Performance to Mitigate Device Aging via a Co-designed Virtual Machine, WDA-3 in conjunction with Micro-41, 2008
A. Pan, J. W. Tschanz, S. Kundu, A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits, Defect and Fault Tolerance in VLSI Systems, 2008
Hyunbean Yi, Sungju Park, and Sandip Kundu, Design-for-Debug (DfD) for NoC- based SoC Debugging via NoC, IEEE Asia Test Symposium, Nov. 2008.
Hyunbean Yi and Sandip Kundu, Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2008.
Hyunbean Yi and Sandip Kundu, On Design of Hold Scan Cell for Hybrid Operation of a Circuit, IEEE European Test Symposium, May 2008.
Aswin Sreedhar and Sandip Kundu, Timing Yield Modeling Based on Simulation of Lithography Process, European Test Symposium, 2008
Aswin Sreedhar and Sandip Kundu, Statistical Yield Modeling for Subwavelength Lithography, International Test Conference, 2008
Kelageri Nagaraj, Sandip. Kundu, An Automatic Post-Silicon Clock Tuning System for Improving Chip Performance Based on Tester Measurements, International Test Conference, 2008
Aswin Sreedhar and Sandip Kundu, Modeling and Analysis of Non-Rectangular Transistors Caused by Lithographic Distortions, Proceedings of ICCD 2008
Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu, On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits, pp. 616-621, DATE 2008
Sandip Kundu, Guiding Light for Chip Testing, DDECS 2008
Alodeep Sanyal, Syed M. Alam, Sandip Kundu, A Built-In Self-Test Scheme for Soft Error Rate Characterization, IOLTS , pp. 65-70, 2008
Alodeep Sanyal, Sandip Kundu, A Built-In Test and Characterization Method for Circuit Marginality Related Failures, ISQED, pp. 838-843, 2008
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu, On Common-Mode Skewed-Load and Broadside Tests, VLSI Design, pp. 151-156, 2008
Kunal Ganeshpure, Sandip Kundu, On ATPG for Multiple Aggressor Crosstalk Faults in Presence of Gate Delays, International Test Conference, 2007
Aswin Sreedhar, Sandip Kundu, On Modeling Impact of Sub-Wavelength Lithography on Transistors, International Conference on Computer Design, 2007
Alodeep Sanyal, Sandip Kundu, On Derating Soft Error Probability Based on Strength Filtering, International On-line Test Symposium, 2007, pp. 152-160
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu, Accelerating Soft Error Rate Testing Through Pattern Selection, International On-line Test Symposium, pp. 191-193, 2007
Ashesh Rastogi, Wei Chen, Alodeep, Sandip Kundu, On Estimating Impact of Loading Effect on Leakage Current in sub-65nm Scaled CMOS Circuits based on Newton-Raphson Method, Design Automation Conference, pp. 712-715, 2007
Ashesh Rastogi, Kunal Ganeshpure, Alodeep Sanyal, Sandip Kundu, Pattern Generation for Composite Leakage Current Maximization, European Test Symposium, 2007
Kunal Ganeshpure, Alodeep Sanyal, Sandip Kundu, A Pattern Selection Approach for Accelerating Soft Error Rate Testing, European Test Symposium, 2007
Ashesh Rastogi, Kunal Ganeshpure, Sandip Kundu, A Study on Impact of Leakage Current on Dynamic Power, ISCAS, pp. 1069-1072, 2007
Kunal Ganeshpure, Alodeep Sanyal, Sandip Kundu, On Accelerating Soft-Error Detection by Targeted Pattern Generation, ISQED 2007, pp. 723-728
Kunal Ganeshpure, Sandip Kundu, Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Cross-Talk Faults, DATE, pp. 540-545, 2007
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu, An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect, VLSI Design , pp. 583-588, 2007
Kunal Ganeshpure, Alodeep Sanyal and Sandip Kundu, A Pattern Generation Technique for Maximizing Power Supply Currents, Int. Conference on Computer Design, 2006
I. Polian, A. Czutro, S. Kundu, and B. Becker, Power droop testing, Int. Conference on Computer Design, 2006
Sandip Kundu, Ilia Polian, An Improved Technique for Reducing False Alarms Due to Soft Errors, International On-line Test Symposium, 2006
Sandip Kundu, A design for failure analysis (DFFA) technique to ensure incorruptible signatures, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Mar 06-10, 2006
Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu, Test Pattern Generation for Power Supply Droop Faults, VLSI conference, India, 2006
Sandip Kundu, Pete Engelke, Ilia Polian, and Bernd Becker, On detection of resistive bridging defects by low-temperature and low-voltage testing, Asian Test Symposium 2005
Sandip Kundu, Matthew D. T. Lewis, Ilia Polian, Bernd Becker, A soft-error emulation system for logic circuits, 20th Conference on Design of Integrated Circuits and Systems, Lisbon, Portugal, 2005
Sandip Kundu, Is the concern for soft-error overblown?, International Test Conference, 2005
Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker, Transient Fault Characterization in Dynamic Noisy Environments, International Test Conference, 2005
Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker, Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies, VLSI Test Symposium, 2005
Sandip Kundu, Is divergence at fault site a necessary condition for fault detection, European Test Symposium 2005
B. Seshadri, I. Pomeranz, S. M. Reddy, S.Kundu, Path-Oriented Transition Fault Test Generation Considering Operating Conditions, European Test Symposium 2005
Sandip Kundu, Matthew D. T. Lewis, Ilia Polian, Bernd Becker, A soft-error emulation system for logic circuits, Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Innsbruck, 2005
Mango C.-T Chao, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu, Static statistical timing analysis for latch-based pipeline designs, ICCAD 2004: 468-472
Sandip Kundu, T. M. Mak, Rajesh Galivanche, Trends in manufacturing test methods and their implications, International Test Conference 2004
C. Tirumurti, S. Kundu, S. Sur-Kolay, Analysis and Modeling of Power Supply Grid, Design Automation and Test in Europe Conference, 2004
M. Naruse, I. Pomeranz, S. Reddy, S. Kundu, On-Chip Compression of Output Responses with Unknown Values Using LFSR Reseeding, International Test Conference 2003
S. Sur-Kolay, C. Tirumurti, S. Kundu, Y. Chang, S. Zachariah, Analysis and Modeling of Power Supply Related Failures, European Test Symposium, 2003
Bill Grundmann, Rajesh Galivanche, Sandip Kundu, Circuit and Platform Design Challenges in Technologies beyond 90nm, Design Automation and Test in Europe Conference, 2003
Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy, On characterization of hard-to-detect bridging faults, Design Automation and Test in Europe Conference, 2003
Sujit Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti, On modeling interconnect cross-talk faults, Design Automation and Test in Europe Conference, 2003
Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy, On Output Response Compression in the Presence of Unknown Output Values, Design Automation Conference, 2002
Sandip Kundu, Chandra Tirumurti, Rathish Jayabharathi, Praveen Parvathala, A Path Delay Fault Simulation System, European Test Workshop, 2002
Sandip Kundu, Sanjay Sengupta, Dhiraj Goswami, Rajesh Galivanche, Constrained Logic BIST for Microprocessors, Design Automation and Test in Europe Conference, 2002
Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic, Fast Statistical Timing Analysis by Probabilistic Event Propagation, Design Automation Conference, 2001
Sitaram Yadavalli, Sandip Kundu, On fault simulation through embedded memories in large industrial designs, 14th International Conference on VLSI Design, pp. 117-121, 2001
Sandip Kundu, Noise: whose problem is it anyway?, International Test Conference, 2000
Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche, Test Challenges in Nano-meter technologies, European Test Workshop, 2000
Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu, Performance Sensitivity Analysis Using Statistical Method and Its Applications to Delay Testing, Asia-Pacific DAC, 2000
Sreejit Chakravarty, Sreenivas Mandava and Sandip Kundu, On Detecting Bridges Causing Timing Failures, International Conference on Computer Design, Austin, Texas, 1999
Sandip Kundu, IDDQ Defect Detection in Deep sub-micron CMOS ICs, Asian Test Symposium, Singapore, 1998
Sandip Kundu, GateMaker: A transistor to gate level extractor for simulation, automatic test pattern generation and verification, International Test Conference, 1998
Sandip Kundu and Uttam Ghoshal, Inductance Analysis of on-chip Interconnects, European Design and Test Conference, Paris, March 1997
Daniel Brand, Anthony Drumm, Sandip Kundu and Prakash Narain, Incremental Synthesis, International Conference on Computer Aided Design, November 1994
Sandip Kundu, Multifault Testable Circuits Based on Binary Parity Diagrams, International Conference on Computer Design, October 1994
A. K. Pramanick and Sandip Kundu, Design of scan-based path delay testable sequential circuits, International Test Conference, October 1993
Sandip Kundu, On Diagnosis of Faults in a Scan-Chain, 11th IEEE VLSI Test Symposium, April 1993
Sandip Kundu and A. K. Pramanick, Testability Preserving Boolean Transforms for Logic Synthesis, 11th IEEE VLSI Test Symposium, April 1993
Sandip Kundu, Indira Nair, Leendert Huisman, Vijay Iyengar and L. N. Reddy, A small test generator for large designs, International Test Conference, pp. 30-40, September 1992
Sandip Kundu and Ankan Pramanick, On testability preserving synthesis transforms, 15th IEEE Workshop on Design for Testability, Vail, Colorado 1992
C. W. Starke, M. Gruetzner, T. W. Williams and S. Kundu, How can biased random pattern test generation yield improved fault coverage for BIST, 14th IEEE Workshop on Design for Testability, Vail, CO, 1991
Roy Thomas and Sandip Kundu, Synthesis of fully testable sequential machines, European Design Automation Conference, February 1991
Sandip Kundu, Indira Nair, Leendert Huisman and Vijay Iyengar, Symbolic implication in test generation, European Design Automation Conference, February 1991
Sandip Kundu, Design of non-systematic 3-SyEC/AUED codes of asymptotically optimal order, International Symposium on Information Theory, San Diego, January 14-19, 1990
Sandip Kundu, A new class of error correcting codes, International Symposium on Information Theory, San Diego, January 14-19, 1990
Sandip Kundu and Sudhakar M. Reddy, Design of TSC checkers for implementation in CMOS technology, Int. Conference on Computer Design, Boston, October 2-4, 1989
Sandip Kundu and Sudhakar M. Reddy, On CMOS Totally-Self-Checking Checkers, First European Workshop on Dependable Computing; Hardware and Software On-line Error Detection, Toulouse, France, March 1-3, 1989
Sandip Kundu, Sudhakar M. Reddy and Niraj Jha, On The Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits IEEE International Conference on Computer Aided Design, Santa Clara, November 1988
Sandip Kundu and Sudhakar M. Reddy, Robust Tests for Parity Trees, International Test Conference, Washington D.C., pp. 680-687, September 1988
Sandip Kundu and Sudhakar M. Reddy, On the Design of Robust Testable CMOS Combinational Logic Circuits, 18th International Symposium on Fault Tolerant Computing, Tokyo, Japan, pp. 220-225, June 1988
Sandip Kundu and Sudhakar M. Reddy, On the Design t-SyEC/AUED Codes, IEEE International Symposium on Information Theory, Kobe, Japan, June 19-24, 1988
Sandip Kundu and Sudhakar M. Reddy, Design of Testable CMOS Circuits, IEEE Design for Testability Workshop, Vail, Colorado, 1988
Sandip Kundu and Sudhakar M. Reddy, On The Design of TSC LFSR Circuits, International Test Conference BIST Workshop, South Carolina, March 11-13, 1987
Sandip Kundu and Sudhakar M. Reddy, On The Design of Embedded TSC Checkers, Proceedings of the 24th Annual Allerton Conference on Circuit and System Theory, October 1986.
Sandip Kundu and Sudhakar M. Reddy, On The Design of TSC CMOS Combinational Logic Circuits, Proceedings of the Int. Conf. on Computer Design, pp. 496-499, October 1986.