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HSPICE tutorial

ECE558/658 FA09 design flow

The contents in this page are linked to NCSU Wiki.

For UMass ECE558/658 students, the environment setup step is not required. The process will be done, when you login to vlsicad. So you don't have to do Create Aliases to Setup Your Environment and Start Cadence Design Framework in NCSU tutorials

After login, you can do "cd vlsix" and "virtuoso&". Now you are ready to follow the tutorials from NCSU. Here is an example.

vlsicad:~>cd vlsix           //The "~" shows that you are at your login directory($HOME).
vlsicad:~/vlsix>               //Now you are at vlsix directory inside your $HOME ($HOME/vlsix).
vlsicad:~/vlsix>virtuoso&    //Now you are executing Cadence Design Framework.

One important thing is that you MUST change your working directory from $HOME to vlsix(by doing "cd vlsix"). This is because of the .cdsinit, cds.lib, lib.defs, and .runset.calibre.xxx files inside in your vlsix directory. Without these files, you will not see any NCSU FreePDK libraries in your Cadence Library Manager, and you will not be able to do DRC, LVS, PEX by using Mentor Graphics Calibre.

o    % add hspice
o    % add synopsys_tools
o    % add_freepdk45

You can simply ignore them.

  • Layout design (Layout editor)
    • In the schematic design tutorial, the library name is ADETutorial, but the library name in Layout design is mylib. You can choose to use different library names for your schematic and layout, but the common practice is using a library name for both.
    • Sample layouts are given here.
  • Layout vs. Schematic Verification(LVS)
    • In the previous tutorials, the circuit was an inverter. However this tutorial starts with a NAND gate schematic example. Because LVS flow for an inverter is the same as a NAND gate, you can use your inverter schematic and layout to follow the LVS flow.
  • Netlist extraction (after layout design) / HSPICE simulation
    • In this tutorial, the actual HSPICE simulation part was not shown, but you can use the extracted netlist to simulate the circuit. Please take a look "Netlist extraction (after schematic design) / HSPICE".
  • Simulation of the netlist extracted from the PEX tool
    • You need to perform the following modifications for the netlist extracted from the PEX tool