FlexGrip: A Synthesizable GPGPU for FPGAs
RTL source code available
The VHDL source code for
this synthesizable core is available upon request. Please contact Prof. Tessier for more information. The core is explained in more
detail in the following publication.
K. Andryc,
M. Merchant, and R. Tessier, FlexGrip:
A Soft GPGPU for FPGAs, in the Proceedings of the
International Conference on Field-Programmable Technology,
Abstract
Over the past decade, soft
microprocessors and vector processors have been extensively used in FPGAs for a wide variety of applications. However, it is
difficult to straightforwardly extend their functionality to support
conditional and thread-based execution characteristic of general-purpose
graphics processing units (GPGPUs) without
recompiling FPGA hardware for each application. In this paper, we describe the
implementation of FlexGrip, a soft GPGPU architecture
which has been optimized for FPGA implementation. This architecture supports
direct CUDA compilation to a binary which is executable on the FPGA-based GPGPU
without hardware recompilation. Our architecture is customizable, thus
providing the FPGA designer with a selection of GPGPU cores which display
performance versus area tradeoffs. The benefits of our architecture are
evaluated for a collection of five standard CUDA benchmarks which are compiled
using standard GPGPU compilation tools. Speedups of up to 30× versus a MicroBlaze microprocessor are achieved for designs which
take advantage of the conditional execution capabilities offered by FlexGrip.
Contact: Russell Tessier (tessier@umass.edu)
More information on the UMass Amherst Reconfigurable Computing Group can be found here.
The FlexGrip
core is released as open-source under the GNU General Public License. THE
SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE