Overview
As FPGAs grow in size there is increased interest in embedding fixed-function networks-on-chip inside the devices. These papers explore NoC issues related to data transfer protocols and I/O interfacing.
We extend recent work on embedded FPGA NoCs fashioned from fixed silicon to consider both dynamic packet-switched and pre-scheduled time-division multiplexed (TDM) routing. The latter approach allows for a reduction in the use of energy-consuming buffers in the FPGA fabric. Our architecture is fully analyzed and the benefits of its use versus packet-switched NoCs are quantified. Multi-fanout nets are shown to particularly benefit from TDM routing.
In our most recent publication we examine routing algorithms for TDM routing. Our approaches consider balancing routing demand across links in the NoC. This balancing allows dynamic packet-switched routing greater access to route links when needed. Performance and energy evaluations of the NoC are performed with a modified NoC simulator.