Advance  Information For TMS320C6201
(summary from TMS320C6201 Data Sheet)

High Performance Fixed-Point Digital Signal Processor (DSP)

  • 5-ns Instruction Cycle Time

  • 200-MHZ Clock Rate

  • Eight 32-Bit Instruction/Cycle

  • 1600 MIPS

VelociTI Advanced Very Long Instruction Word (VLIW) 62x CPU core
  • Eight Highly Independent Functional Units:  Six ALUs (32-/40-Bit) Two 16-Bit Multipliers (32-Bit Results)

  • Load-Store Architecture With 32 32-Bit General-Purpose Registers

  • Instruction Packing Reduces Code Size

  • All Instructions Conditional

Instruction Set Features
  • Byte-Addressable (8-, 16-, 32-Bit Data)

  • 32-Bit Address Range

  • 8-Bit Overflow Protection

  • Saturation

  • Bit-Field Extract, Set, Clear

  • Bit Counting

  • Normalization

1M-Bit On-Chip SRAM
  • 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)

  • 512K-bit Dual-Access Internal Data (64K Bytes)

32-Bit External Memory Interface (EMIF)
  • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM

  • Glueless Interface to Asynchronous Memories: SRAM and EPROM

Four -Channel Bootloading Direct Memory Access (DMA) Controller with an Auxiliary Channel
16-Bit Host Port Interface (HPI)
  • Access to Entire Memory Map

Two Multichannel Buffered Serial Ports
  • Direct Interface to T1/E1, MVIP, SCSA Framers

  • ST Bus Switching Compatible

  • Up to 256 Channels Each

  • AC97-Compatible

  • SPI-Compatible

Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan Compatible
352-Pin BGA Package
3.3-V I/Os, 2.5-V Internal

More detail can be found in TMS320C6201 Data Sheet and websites:
http://www.ti.com/sc/docs/dsps/products/c6000/c62x/arch.htm
http://www.ti.com/sc/docs/dsps/products/c6000/c62x/201feat.htm

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