In the previous project, we learned how to interface the 16F877 microcontroller to a dumb terminal. In this assignment the focus is twofold. To make things interesting, you will also program an on-chip timer to generate periodic interrupts that toggle an output signal attached to bit 2 of port C. Additionally, you will develop an external "bus" interface between your PIC device and an external PLD. This is the first step towards building a complete PIC system including external memory which you will tackle in lab 3. This lab will not only involve the development of PIC assembler code, but also the development of a significant amount of VHDL code to program the PLD. VHDL rather than Altera schematics must be used for this assignment.
In order to be checked off the following tasks must be completed. For additional information regarding these tasks, please see the lecture notes for Lab 2.
1. Your microcontroller should be programmed to generate a timer interrupt from Timer 0 (TMR0) every .0327 seconds. For EVERY OTHER timer interrupt, the polarity of the output signal bit 2 of Port C should be toggled. This bit should be attached to an LED so that toggling is apparent. As discussed in lecture, the code to toggle the value of the bit should be included in an interrupt service routine. Be sure to show how you determined the prescalar value for Timer 0 in your lab report. The interrupts and bit toggling should happen independently of any other code running on your 16F877
2. As discussed in lecture, Ports A. B, C, and D of your PIC should be interfaced to a 7032 PLD. Ports A, B, and D are used to transfer address and data values between the PIC and PLD devices and individual bits on Port C can be used for control. Please be careful to configure data direction registers accordingly. Avoid using bits 2, 6, 7 on Port C for your PIC/PLD interface since they will be used by the toggle LED (bit 2) and UART (bits 6, 7) respectively.
3. After physically wiring the PIC to the PLD, write READ and WRITE macros or subroutines in assembler that allow for data transfer between the two parts.
4. Program the PLD to allow the transfer of both address and data values between the PIC and PLD. For this assignment four bits of address will be used. As discussed in class, build state machines to allow for reliable transfer of first address and then data. In order to be checked off you need to show interface signals on the logic analyzer corresponding to both transactions. Note that depending on how you decide to implement the design you may require two PLDs for the implementation.
5. One switch should be attached to a PLD input and four LEDs should be attached to PLD outputs. Both of these locations can be accessed at address 0x2 in the PLD (read for the switches, write for the LEDs). Additionally, a four-bit counter should be allocated inside the PLD. This register can be either read or written and is located at address 0x9. The PIC can read/write the switches/LED by sending an address of 0x2 to the PLD along with appropriate address/data signals. The PIC can read the four-bit counter by sending an address of 0x9 to the PLD along with appropriate address/data signals. Note that transfers between the PLD switches and LEDs should be performed by the PIC not by the PLD code.
6. If the switch is in the on position (value is binary 1) the counter should increment on every PLD clock cycle. If the switch is in the off position (value is binary 0) the counter should maintain its current value and not increment. The initial value of the counter is unimportant.
7. As explained below, when a value on the switch attached to the PLD changes, the message "Counter value: #" should be sent by the PIC to the terminal. The string ("Counter value:") displayed on the terminal should be included in your code using the 'dt' directive discussed in class. The "#" should be the hex value of the four bit counter.
8. Your completed system should operate in stand-alone mode for checkoff.
In order to be checked off your PIC should be continuously sharing data with the PLD as described below. Periodically, Timer 0 will generate an interrupt which causes the LED connected to Port C, bit 2 to be toggled. There really are three pieces of code that need to be written for this assignment: the timer initialization and interrupt service code which reads and toggles the bit attached to Port C, the VHDL code for the PLD, and a loop for the PIC which continuously reads the counter value and writes LED values to the PLD. The following describes the behavior of the basic code loop running on the PIC which will interact with the PLD and the VHDL code for the PLD.
1. The PIC reads the counter value in the PLD by performing a read transaction to PLD address 0x9. The four bit value is transfered to the PIC using handshaking.
2. The PIC reads the switch value attached to the PLD by performing a read transaction to PLD address 0x2. The single bit value is transfered to the PIC using handshaking.
3. The PIC compares the read switch value to the value that was previously read during the previous iteration of the loop. If a difference is noted, a message including the COUNTER value is sent to the terminal through the UART which reads "Counter value: #" (don't forget to use 'dt'). For the first switch comparison, assume the "previous value" is 0.
4. Regardless of whether the switch value is new or not, a value of 1 IS ADDED TO THE READ VALUE of the counter and the result is sent to the PLD for display in the LEDs (PLD address 0x2) via a write transaction. Note that since the value consists of 4 bits, the value may "wrap around" (e.g. switches = 0xF, LED display is 0x0).
1. Make sure you have set the PLD I/O pins correctly before programming the parts. Take all unused inputs into account.
2. Make sure that handshaking is handled appropriately. This may require several clock cycles. Designs that work "some of the time" are not acceptable. Data transfer must be successful every time.
The demonstration should show communication between the EPLD and the 16F877 on the logic analyzer. The switches and LEDs attached to the PLD should follow the same conventions as lab 1.
Your report should include the two logic analyzer printouts (one read transaction, one write transaction), a source listing of your assembly code and PLD code and a discussion of your design and of any problems found and their resolution. The report should follow the same format as the lab 1 report. Be sure to include detailed schematics of your design including pin numbers and signal names.