Contributors
The RAID tutorial was prepared by Ravinder Rachala and Prashant Jain as a final project in the Fall 1999 Computer Architecture course.
The single task reservation table analyzer was prepared by Qiang Yu as a final project in the Fall 1998 Computer Architecture course.
The two-task reservation table analyzer was prepared by Thomas Chou as a final project in the Fall 1999 Computer Architecture course.
The Cache Demonstrator was prepared by Geoff Gallo and Navin Vemuri as a final project in the Fall 1999 Computer Architecture course.
The Transaction Processing example was prepared by Giyasettin Ozcan as a final project in the Fall 1999 Computer Architecture course.
The memory interleaving tool was prepared by Rajnish Prasad as a final project in the Fall 1999 Computer Architecture course.
The scoreboarding tool was prepared by Rishi Khasgiwale and Vishak Venkatarman as a final project in the Fall 2002 Computer Architecture course.
The pipelining tool was prepared by Ian DeAngelis as a final project in the Fall 2002 Computer Architecture course.
The reorder buffer tool was prepared by Felix Werth as a final project in the Fall 2002 Computer Architecture course.
The VLIW tutorial was prepared by Chris Carnell and Kenji Ross as a final project in the Fall 2003 Computer Architecture course.
The Java-based Tomasulo tool was prepared by Daniel F. Gomez Prado as a final project in the Fall 2003 Computer Architecture course.
The Javascript-based Tomasulo tool was prepared by Hemant Kumar as a final project in the Fall 2002 Computer Architecture course.
The virtual memory simulator was prepared by Shashank Gupta and Akash Goel as a final project in the Fall 2003 Computer Architecture course.
The branch prediction simulator was prepared by Venkata Avasarala as a final project in the Fall 2003 Computer Architecture course.
The Cache Demonstrator was prepared by Eric Fallon as a final project in the Spring 2004 Computer Architecture course.
The Static vs. Dynamic Pipeline Scheduling module was prepared by Niranjan as a final project in the Fall 2004 Computer Architecture course.
The Cache Energy Estimation module was prepared by Atchuthan Perinkulam as a final project in the Fall 2004 Computer Architecture course.
The Cache-TLB simulation module was prepared by Siddhartha Bunga and Rakesh Kothari as a final project in the Fall 2004 Computer Architecture course.
The vector processor simulation module was prepared by Jun Fan as a final project in the Fall 2004 Computer Architecture course.
The disk scheduling for performance and energy module was prepared by Ruchika Singh and Sameer Ladiwala as a final project in the Fall 2004 Computer Architecture course.
The branch target buffer simulator was prepared by Sugam Pandey as a final project in the Fall 2005 Computer Architecture course.
The Java-based page replacement policies simulator was prepared by Nicholas Merrill as a final project in the Fall 2005 Computer Architecture course.
The loop unrolling simulator was prepared by Kunal Ganeshpure as a final project in the Fall 2005 Computer Architecture course.
The Scheduling of real-time tasks for energy simulator was prepared by Venkatesh Shanbhag as a final project in the Fall 2005 Computer Architecture course.
The victim cache simulator was prepared by Sumana Mannem as a final project in the Fall 2005 Computer Architecture course.
The voltage scaling simulator was prepared by Soumya Mahadevan as a final project in the Fall 2005 Computer Architecture course.
The dual cache simulator was prepared by Amrit Kumar as a final project in the Fall 2005 Computer Architecture course.
The XOR cache simulator was prepared by Suraj Jaiswal as a final project in the Fall 2005 Computer Architecture course.
The SimpleScalar Lab experiments were prepared by Tariq Bashir Ahmad as a final project in the Fall 2006 Computer Architecture course.
The selective victim cache simulator was prepared by Aparna Venkataramani as a final project in the Fall 2006 Computer Architecture course.
The I-cache energy and temperaure simulator was prepared by Basab Datta and Aswin Sreedhar as a final project in the Fall 2006 Computer Architecture course.
The loop unrolling in VLIW simulator was prepared by Pooja Subrama as a final project in the Fall 2006 Computer Architecture course.
The M-Simple Lab experiments were prepared by Jai Gupta as a final project in the Fall 2006 Computer Architecture course.
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