Welcome to Tariq Bashir Ahmad's Web Space


Tariq Bashir Ahmad
PhD 
Advisor: Professor Maciej Ciesielski            

 resume.pdf                                                  
Email:   tbashir'at'ecs'dot'umass'dot'edu, tariq'dot'bashir'at'gmail'dot'com

 
Introduction

I am PhD in Electrical and Computer Engineering focusing in the areas of hardware verification and security engineering.

Education
  • 01/2008 - 12/2013:            PhD in Electrical and Computer Engineering                                                                                               
                                               VLSI CAD Lab, University of Massachusetts Amherst                                              
  • 09/2004 - 07/2007:            M.S. in Electrical and Computer Engineering                                                                        
                                               VLSI CAD Lab, University of Massachusetts Amherst
  • 8/1996 - 06/2000:               B.S. in Electronic Engineering                                                       
                                               GIK Institute of Engineering and Technology, Pakistan
Research
  • Accelerating hardware description language (HDL) simulations
  • Architecture and implementation of Cryptographic algorithms
Professional Experience

·        10/2011 - 12/2013:           Research Assistant, VLSI CAD Lab, University of
                                          Massachusetts Amherst


 Dissertation Title: Parallel Multi-core Verilog HDL Simulation

 

·        9/2011 - 12/2011,

1/2014 - 05/2014:             Teaching Assistant, ECE Department, University of
                                          Massachusetts Amherst

 Teaching assistant for digital logic design (undergraduate course) and Computer Algorithms (graduate course).

 

·     6/2011 - 10/2011               Intern Hardware Formal Verification Group, Apple  
                                               Computers, Cupertino, CA
                                                                                                                    

   
a) Formal verification of design library components. 
   b) Formal verification of System on a chip (SoC) bridge protocols.
   c) Implemented formal scoreboards for checking in-order and out-of-order data integrity.
   d) Formally verification of SoC 2x1 bus switch.

 

  • 9/2009 - 10/2010                    Intern, Ethernet R&D, Marvell Semiconductor, Santa
                                                    Clara, CA.                       
                                                                                                                      
      
    a) Federal Information Processing Standards (FIPS) validation of 1 Gbps and 10 Gbps Ethernet
            Security hardware solutions. Development of reference model of Galois Counter Mode-     
            Advanced Encryption Standard (GCM-AES). 
       b) Development of Assembly Parser for MACSEC engine instruction set architecture (ISA).
       c) Development of MACSEC engine Instruction set simulator in C.
       d) Field Programmable Gate Array (FPGA) emulation of MACSEC core on Xilinx Virtex 6   
           FPGA.

 

Projects and Case Studies
  1. Accelerating RTL, Gate level Functional (zero-delay) and timing simulations (PhD Thesis)
  2. HDMI to Ethernet converter (Accepted Google Summer of Code Project) Link
  3. Verification of digital arithmetic circuits using Linear Algebra Methods  Link 
  4. Hardware Design and Implementation of Galois Counter Mode AES (GCM-AES) mode of Operation Link (Active)
  5. Hardware Design and Implementation of Offset Code Book 3 (OCB3) mode of Operation Link  (In Progress)
  6. Hardware Design and Implementation of high performance AES Encryption cores Link (Active)
  7. Custom Cell Design of ASIC gates. Link   (Active)
  8. Standard Cell Design of ASIC circuits. Link (Active)
  9. FGPA Implementation of various algorithms. Link (Active)
  10. Timing Attack on RSA Implementation. Link (Active)
  11. Estimation of maximum Power Supply Current in large CMOS circuit based upon compact switching model (MS Thesis) Link (Active)
  12. Development of lab exercises for graduate Computer Architecture course using SimpleScalar. The labs have received recognition from the University of Texas Austin. Link (Active)
  13. Parsing ISCAS-85 Benchmarks for Fault Simulation. Link (Active)
  14. IIR and FIR filter Design with coefficient quantization in MATLAB. Link (Active)
  15. Implementation of Computer Vision Algorithms for Image warping, Edge detection and Motion Detection in C++. Link (Active)
  16. Security and Privacy in Context-Aware Computing in Healthcare.  (Case Study) Link (Active)
  17. Efficient RTL Synthesis of DSP Algorithms.     (Case Study) Link (Active)
  18. Prototype of IPHONE Medical Calculator. Link (Active)
Computer Skills
Programming: C,  Python, Java
HDL: Verilog,
Parser: Flex & Bison
EDA CAD Tools: (Simulation) HSpice, VCS, NC-Verilog. (Layout) SoC Encounter, Virtuoso, Astro. (Formal Verification) JasperGold, Formality
Solvers: Lingo, MATLAB, NumPy
FPGA: Xilinx ISE tool suite
Embedded: Atmel AVR, Iphone Programming
Operating System: Linux, Windows, MAC
Version Control: Git  (Github Repository)
Editor: Latex
Papers
  • Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej Ciesielski,"Algebraic approach to arithmetic design verification," Formal Methods in Computer Aided Design (FMCAD) 2011
  • Tariq Bashir Ahmad, Namdo Kim, Byeong Min, Apurva Kalia, Maciej Ciesielski, Seiyang Yang, "Scalable parallel event-driven HDL simulation for multi-cores," SMACD 2012
  • Tariq Bashir Ahmad, Dusung Kim, Maciej Ciesielski, Seiyang Yang, "Application of Parallel Distributed Event-Driven Simulation for Accelerating Hardware Verification," ADPC 2012
  • Tariq B. Ahmad, and M. Ciesielski, "An Approach to Multi-core Functional Gate-level Simulation Minimizing Synchronization and Communication Overheads," Microprocessor Test and Verification Conference, (MTVCON 2013)
  • Tariq B. Ahmad, and M. Ciesielski, "Fast STA Prediction-based Gate-level Timing Simulation,"Design and Test Europe, (DATE) 2014
  • Tariq B. Ahmad, and Maciej Ciesielski, "Fast Time-Parallel C-based Event-Driven RTL Simulation," Design and Diagnostics of Electronic Circuits (DDECS) 2014, Poland.
  • Tariq B. Ahmad, and Maciej Ciesielski, "Parallel Multi-core Verilog HDL Simulation using Domain Partitioning," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, Florida, 2014
     
Trainings, Workshops and Conferences
  • Shmoocon Security Conference, Jan 17-19 2014, Washington DC.
  • Python for Scientists and Engineers, Dec 9 - 13 2013, Austin, Texas.
  • NetFPGA Summer Camp at Stanford University, July 29 - Aug 2 2013, California (Slides) (News)
  • SANS Security Essentials Boot camp, June 17-22 2013, Washington DC.
  • Advanced Python Mastery with David M. Beazley, May 6-10 2013, Chicago
  • Pycon 2013, March 2013, Chair of sessions on Introduction to Cryptography 101 and Python Software Foundation, Santa Clara, California
  • SRI Summer School on Formal Methods for Hardware and Software Verification, May 2012, Atherton, California
  • Xilinx FPGA Design Fundamentals, May 2009, Xilinx Headquarter, San Jose, California.
  • Xilinx Design for Performance, December 2009, Xilinx Headquarter, San Jose, California.
  • Xilinx Advanced FPGA Design, May 2009, Xilinx Headquarter, San Jose, California.
  • Xilinx Design with Planahead, May 2009, Xilinx Headquarter, San Jose, California.
  • Sun Burst Design's Comprehensive Verilog, September 2009, Sun Burst Design, Milpitas, California.
  • ALTERA Advanced Verilog Design Techniques, December 2009, Altera Headquarter, San Jose, California.
  • SYNOPSYS Design Compiler, December 2009, Synopsys Headquarters,Mountain View, California.
  • SYNOPSYS System Verilog, May 2011, Synopsys Headquarters, Mountain View, California.
  • SANS Reverse Engineering Malware, July 2010, SANS Security West, San Diego, California.
  • SANS Penetration Testing, January 2009, SANS Security West, Las Vegas, Nevada.
  • Black Hat's Man in the Middle in Secure Communications, August 2009, Las Vegas, Nevada.
  • IPhone Barcamp, April 2008, New York city, New York

     

    Open source Contributions

     

  • Active serving community member at edaboard.com for over a decade (Link)

  • Opensource hardware implementations of  line rate encryption engines for 10 Gbps NetFPGA  (Awarded Best Project on August 2, 2013 at Stanford NetFPGA Conference) (Slides) (News)

  • Organizer of Openhatch.org opensource programming and bugfixing workshop, April 2013, UMASS Amherst (Link)

  • Opensource hardware implementations of fast AES-128 algorithm (Link)

  • Opensouce hardware implementation of low area GCM-AES (Link)

  • Worked on documentation and portability of tahoe-lafs (tahoe least authority file system) during Pycon 2013 sprint. This will continue (Link)

  • Working on bug fixing opensource projects at openhatch.org (Link)

  • Volunteer at Wearable Electronic Workshop for kids using Arduino microcontroller, Holyoke Youth center, Feb 2013, Holyoke, MA

     

    Awards

  • Best Project Award, NetFPGA Summer Camp at Stanford University, August 2013 (Slides) (News)

  • William J. Fulbright scholar (US State Department Scholarship) at the University of Massachusetts Amherst (2004 – 2009)

     

     

    Buying Links