1. R.Rodrigues, I.Koren and S.Kundu, “Does the Sharing of Execution Units Improve Performance/Power of Multicores?” To appear in ACM Transactions on Embedded Computing Systems (TECS) (accepted) 2014.
2. Abhisek Pan, Rance Rodrigues and Sandip Kundu, “A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors,” To appear in ACM Transactions on Embedded Computing Systems (TECS) (accepted) 2014.
3. Kunal Ganeshpure and Sandip Kundu. 2014. Performance-driven dynamic thermal management of MPSoC based on task rescheduling. ACM Trans. Des. Autom. Electron. Syst. 19, 2, Article 11 (March 2014), 33 pages.
4. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel, "Globally Constrained Locally Optimized 3D Power Delivery Networks," IEEE Transactions on VLSI Systems
5. R.Rodrigues, A.Annamalai, I.Koren and S.Kundu. A Study on the use of Performance Counters to Estimate Power in Microprocessors. IEEE Transactions on Circuit and Systems II
6. Kunal Ganeshpure and Sandip Kundu, “Game theoretic Approach for Run-time Task Scheduling on an MPSoC,” to appear in Journal of IET Circuits, Devices & Systems, 2013
7. R. Rodrigues, A. Annamalai, and S. Kundu. "A Low Power Instruction Replay Mechanism for Design of Resilient Microprocessors". ACM Transactions on Embedded Computing Systems (TECS) Article 85, 23 pages, March 2014,
8. A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo, A. Virazel, “A Study of Tapered 3D TSVs for Power and Thermal Integrity,” IEEE Transactions on VLSI, Feb. 2013, pp. 306-319
9. Rance Rodrigues, Arunachalam Annamalai, Israel Koren, and Sandip Kundu, “Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing,” ACM Transactions on Design Automation of Electronic Systems, Vol. 18, No. 1, pp. 5:1-5:23, January 2013
10. Alodeep Sanyal, Kunal Ganeshpure, Sandip Kundu, “Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading from Fanout Nodes in Presence of Gate Delays," IEEE Transactions on VLSI, vol. 20, number 3, 2012, pp. 424-436.
11. Aswin Sreedhar, Sandip Kundu and Israel Koren, “On Reliability Trojan Injection and Detection,” Journal of Low Power Electronics, vol 8, number 5, 2012, pp. 674-683
12. Omer Khan and Sandip Kundu, “An Empirical Model for Cooperative Resizing of Processor Structures to Exploit Power-Performance Efficiency at Runtime,” Journal of IET Circuits, Devices & Systems, September 2012, pp. 355 - 365
13. Sudarshan Srinivasan, Kunal P Ganeshpure, Sandip Kundu, "A Wavelet based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip" Vol. 31, No. 12, pp. 1867-1880, December 2012.
14. Kunal Ganeshpure, Alodeep Sanyal and Sandip Kundu, "A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays," IEEE Transactions on Computers, vol. 61, no. 7, pp. 986-998, July 2012
15. Michael Buttrick, Sandip Kundu, "On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs," Journal of Electronic Testing, vol. 28, pp: 93-101, Feb 2012
16. Omer Khan and Sandip Kundu, “Hardware/Software Co-design Architecture for Online Testing in Chip Multiprocessors,” IEEE Transactions on Dependable and Secure Computing, pp. 714-727, September/October, 2011.
17. Omer Khan and Sandip Kundu, “Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors,” Transactions on High-Performance Embedded Architectures and Compilers, Volume 4, LNCS 6760, pp. 84-110, 2011
18. Alodeep Sanyal, Syed M. Alam and Sandip Kundu, "Built-In Self-Test for Detection and Characterization of Transient and Parametric Failures," IEEE Design and Test, vol 27, number 5, 2010, Pages 50-59
19. Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey, "Test Pattern Generation for Droop Faults," IET Comput. Digit. Tech, vol 4, 2010, Pages 274-284
20. Omer Khan, Sandip Kundu, "Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors," IEEE Transactions on Computers, pp. 651-665, May, 2010.
21. Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu. “An Efficient Technique for Leakage Current Estimation in Nano-Scaled CMOS Circuits Incorporating Self-loading Effects," IEEE Transactions on Computers, vol 59, number 7, 2010, Pages 922-932
22. Kunal P. Ganeshpure and Sandip Kundu, "On ATPG for Multiple Aggressor Crosstalk Faults,", IEEE Transactions on CAD, vol. 29, pp. 774-787, May 2010
23. Hyunbean Yi, Sungju Park, and Sandip Kundu, "On-Chip Support for NoC-based SoC Debugging," IEEE Transactions on Circuits and Systems I, vol 57, number 7, 2010, Pages 1608-1617
24. Hyunbean Yi, Sandip Kundu, S. Cho and S. Park, "A Scan Cell Design for Scan-based Debugging of an SoC with Multiple Clock Domains, IEEE Transactions on Circuits and Systems II, vol 57, No 7, 2010, Pages 561-565
25. R. A. Shafik, B. M. Al-Hashimi, S. Kundu, A. Ejlali, “Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific MPSoC,” Journal of Low Power Electronics, August 2009
28. Ashesh Rastogi,
Kunal P. Ganeshpure,
Engelke, Ilia Polian. Michel Renovell,
Sandip Kundu, Bernd Becker, Bharath Seshadri, and
30. Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker, "Power Droop Testing," IEEE Design and Test of Computers, vol. 24, no. 3, pp. 276-284, May-June, 2007
32. Sandip Kundu, Sujit Zachariah, Yi-Shing Chang, Chandra Tirumurti, “On modeling interconnect cross-talk faults”, IEEE Transactions on CAD, vol. 24 , no. 12, Dec. 2005, pp. 1909 – 1915
34. Sandip Kundu, “Pitfalls of Hierarchical Fault Simulation”, IEEE Transactions on CAD, February 2004, pp. 312- 314
36. Sandip Kundu, Sujit Zachariah, Sanjay Sengupta and Rajesh Galivanche, “Test Challenges in Nanometer Technologies”, Journal of Electronic Testing: Theory and Applications, pp. 209-218, 2001
37. Sanjay Sengupta, Sandip Kundu, Sreejit Chakravarty, Praveen Parvathala, Rajesh Galivanche, George Kosonocky, Mike Rodgers, and TM Mak, “Defect-Based Test: A Key Enabler for Successful Migration to Structural Test”, Intel Technical Journal, 1999 1st quarterly issue
38. Sandip Kundu, E. S. Sogomonyan and M. Goessel, “Self-checking comparator with one periodic output”, IEEE Transactions on Computers, vol. 45, no. 3, March 1996
39. Sandip Kundu, “On construction of non-systematic t-symmetric error correcting/ all unidirectional error detecting codes”, IEICE Transactions on Inf. System, vol. E78-D, No. 5, May 1995
40. Sandip Kundu, “An incremental algorithm for identification of longest (shortest) paths”, Integration, pp. 25-31, vol. 17, 1994
41. Sandip Kundu, “An efficient technique for obtaining unate implementation of functions through input encoding”, Integration, pp. 265-270, vol. 17, 1994
42. Leendert Huisman and Sandip Kundu, “Highly reliable symmetric networks “, IEEE Trans. on Parallel and Distributed Processing”, pp. 94-97, Jan 1994
43. Sandip Kundu, “Diagnosing Scan Chain Faults”, IEEE Transactions on VLSI Systems, pp. 512-516, vol. 2, No. 4, December 1994
48. Sandip Kundu, “Design of Multi-output CMOS Combinational Logic Circuits for Robust Testability,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 1222-1226, November 1989