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Personal Information
Education background
Research

Labs for ECE658 VLSI Design Principles
Lab 1
Lab 2
Lab 3
Lab 4

My current research project

On-Chip Sensing Strategies for Efficient and Robust Scalability in Many-Core Architectures

More information about this project upon request

Previous research project

MNoC: A Monitor Network-on-chip for Configurable Monitors

Publications

1.    J. Zhao, R. Vadlamani and R. Tessier, “Energy-Efficient Adaptive Redundancy for Multicore Soft Error Remediation”, preparing manuscript.

2.         J. Zhao, S. Madduri, R. Vadlamani, W. Burleson and R. Tessier, "A Dedicated Monitoring Infrastructure for Multicore Processors," in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), to appear, 2010. (pdf)

3.         J. Zhao, B. Datta, W. Burleson and R. Tessier, "Thermal-aware Voltage Droop Compensation for Multi-core Architectures," in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI'10), pp. 335-340, May 2010. (pdf)

4.         R. Vadlamani, J. Zhao, W. Burleson and R. Tessier, "Multicore Soft Error Rate Stabilization Using Adaptive Dual Modular Redundancy", in Proc. of Design, Automation and Test Europe(DATE'10), pp. 27-32, 2009. (pdf)

5.         D. Unnikrishnan, J. Zhao, R. Tessier, "Application-specific Customization and Scalability of Soft Multiprocessors", in Proc. of Field Custom Computing Machines Conference (FCCM'09), pp. 123-130, 2009. (pdf)

6.         Liang Li, Jun Han, Xiaoyang Zeng, J. Zhao, "A Full-custom Design of AES SubByte Module with Signal Independent Power Consumption", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'08), pp.3302-3305, 2008. (pdf)

7.         Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, and J. Zhao, "A Low-Cost Cryptographic Processor for Security Embeded System", in Proc. of Asia and South Pacific Design Automation Conference(ASP-DAC'08), pp. 113-114, 2008. (pdf)

8.         J. Zhao, Jun Han, Xiaoyang Zeng, Jun Chen, "VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack", in Proc. of International Conference on ASIC (ASICON'07), vol. 2, pp. 838-841, 2007. (pdf)

9.         J. Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng, "Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation", in Proc. of IEEE Workshop on Signal Processing and System(SIPS'07), pp.151-156, 2007. (pdf)

10.      Yehua Gu, Xiaoyang Zeng, Jun Han, J. Zhao, "A Low-Cost and High-Performance SoC Design for OMA DRM2 Applications", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'07), pp. 3510-3513, 2007. (pdf)

11.     J. Zhao, Xiaoyang Zeng, Jun Han, Jun Chen, "Very Low-cost VLSI Implementation of AES Algorithm", in Proc. of Asian Solid-State Circuits Conference (ASSCC'06), pp.223-226, 2006. (pdf)

12.     J. Zhao, Xiaoyang Zeng, Jun Han, Jun Chen, "Simplified AES Algorithm Resistant to Zero-Value Power Analysis and its VLSI Implementation", in Proc. of International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'06), vol. 3, pp. 1937-1940, 2006. (pdf)

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