North Atlantic Test Workshop

Advance Program
IEEE 10^th North Atlantic Test Workshop 2001

THURSDAY, MAY 24

8:20 AM - 8:30 AM Greetings
8:30 AM - 9:30 AM Invited Talk: ``An ATE Manufacturer's Perspective on DFT Tester Development'', Song Lee - Teradyne
9:45 AM - 11:45 AM Session 1: HDL Test
1. ``A High-Level Fault Simulation Methodology for Complex VLSI Designs'', Bryan J. Gran, Carol Stolicny - Compaq
2. ``Study of the Relationship Between High Level and Logic Level Vector Sets'', Aaresh Powvalla, Ganapathy Kasturirangan, Liang Zhang, Michael S. Hsiao - Rutgers U.
3. ``SPC-FS: A New Method for Fault Simulation Implemented in VHDL'', M. Zolfy, S. Mirkhani - U. of Tehran, Z. Navabi - Northeastern U.
4. ``Test Bench and BIST Architecture Evaluation Environment in VHDL'', H. Farshbaf, S. Mirkhani, M. Zolfy - U. of Tehran, Z. Navabi - Northeastern U.
11:45 AM - 1:00 PM --- Lunch
1:00 PM - 4:00 PM --- Social Event
We will take a group excursion to the town of Rockport at the northern-most tip of Cape Ann. A host of interesting shops and galleries surround Rockport's charming harbor, which is still home to an active fishing fleet. Rockport is one of the country's oldest artist colonies, and boasts some of the most widely painted seaside landscapes in the world, including the coastal shack known as Motif 1.
4:00 PM - 5:30 PM Session 2: Memory Test
1. ``Parallel Testing of Dual-Port Static Random Access Memories'', F. Karimi, S. Irrinki, T. Crosby, F. Lombardi - Northeastern U.
2. ``Testing Methodology for the PowerPC 440 Embedded Arrays'', Waleed K. Al-Assadi - IBM
3. ``Defect Analysis and Realistic Fault Model Extensions for Multi-Port SRAMS'', Pradeep Nagaraj, Shambu Upadhyaya - SUNY Buffalo, Kamran Zarrineh - Sun Microsystems, Dean Adams - IBM
5:45 PM - 6:45 PM Invited Talk: ``Test Generation, Fault Simulation, and Diagnosis Using Fault Tuples'', Shawn Blanton - Carnegie Melon University
6:45 PM - 8:15 PM --- Dinner
8:15 PM - 10:15 PM Tutorial:
``Recent Developments in Logic Verification'', Dhiraj Pradhan - Oregon State University,USA and University of Bristol,UK

FRIDAY, MAY 25

8:00 AM - 9:00 AM Keynote Speaker: Yervant Zorian - Logic Vision Inc.
9:15 AM - 10:45 AM Session 3: High-Level Fault Modeling
1. ``An Experimental Investigation on the Accuracy of Stratified RTL Fault Coverage'', Pradip Thaker - Fujitsu Labs of America, Vishwani Agrawal - Agere Systems, Mona Zaghoul - George Washington University
2. ``Optimizing Frequency and Identifying Failure Modes'', Alexander J. Porter - Entela Inc.
3. ``Behavioral Fault Modeling of Analog Circuits'', Yu-Yao Guo, Jien-Chung Lo - U. of Rhode Island
11:00 AM - 12:30 PM Session 4: Defect and Parametric Test
1. ``Determining Repeatable Semiconductor Chip Yield Detractors Using LBIST Failing Signatures'', Richard F. Rizzolo, Peilin Song - IBM
2. ``Short or Open? - A Diagnostic Story'', Peilin Song, Franco Motika, William Huott, Julie Lee, Raymond Mallette - IBM
3. ``Fitting Tester Yield Curves'', Jose T. de Sousa - IST/INESC, Technical University of Lisbon, Vishwani D. Agrawal - Agere Systems
12:30 PM - 1:45 PM --- Lunch
1:45 PM - 3:15 PM Session 5: Reliable System Test
1. ``Testing Distributed Real Time Systems Using a Centralized Test Architecture'', Ahmed Khoumsi - U. of Sherbrooke
2. ``Timing Covalidation of Hardware/Software Systems'', Qiushuang Zhang, Ian G. Harris - U. Massachusetts
3:30 PM - 5:00 PM Session 6: DFT and BIST
1. ``Relationship Between Logic Test Sets and Bridging Fault Detection in IDDQ Environment'', Suntae Hwang - Taejon University
2. ``Scan Islands - An Architecture for Cost-Efficient Scan Testing of High Performance VLSI Circuits'', Dilip K. Bhavsar, Richard Davies - Compaq
3. ``A Hierarchical Approach to Improving Random Pattern Testability on IBM eServer z900 Chips'', Richard F. Rizzolo, Bryan J. Robbins, David G. Scott - IBM