ECE 697PP: Design for Manufacturability and Reliability of VLSI Circuits

Professor Sandip Kundu

 

Office Hours: Tuesday, 1:30 PM Ė 2:30 PM
Knowles Engineering Building, 309J
(413) 577-3309

Class: TuTh  11:15AM - 12:30PM Marcus Hall room 106

Textbook (Recommended): Nanoscale CMOS VLSI Circuits: Design for Manufacturability, Sreedhar & Kundu, ISBN 978-0071635196, McGraw-Hill Professional; 1 edition (June 17, 2010)

Supplementary Readings:

1.    Fundamental Principles of Optical Lithography: The Science of Microfabrication, Chris Mack, ISBN 978-0470727300

2.    Principles of Lithography, Second Edition, Harry Levinson, ISBN 978-0819456601

3.    Israel Koren, C. Mani Krishna, "Fault-Tolerant Systems," Morgan Kaufmann (March 15, 2007), ISBN: 978-0120885251

Grading:

  • Presentation of papers in class - 25%
  • Presentation report (concentrating on criticism and suggestions for improvements/extensions) - 15% 
  • Attendance and participation - 20% (you should read the papers to be presented by other students, before the class, in order to participate in the discussion.)
  • Final project - 40%

Course Objectives:

This is a second level course in VLSI Design, exploring Design for Manufacturability and Design for Reliability issues in nano-scale CMOS circuits. At the end of this course, students will gain understanding of Layout Enhancement for Manufacturability (LEM) techniques to improve manufacturability. In Design for Reliability, this course is primarily focused on reliability analysis and reliability improvement techniques at the schematic and layout levels.

Course Description:

The course will cover basic theory and practices in DFM and circuit level DFR. Topics include: Lithography trends, Lithography simulation, Resolution enhancement techniques (RET) such as optical proximity correction (OPC), phase shift masking (PSM), source-mask optimization (SMO), dual pattern lithography (DPL) and inverse lithography technique (ILT). Design rules checking (DRC) involving geometric design rules (GDR), restricted design rules (RDR) and Design Rules Manual (DRM). Origin of rules from exposure, etch, alignment, chemical mechanical polishing and charge collection. Various metal and physical fill techniques. Defect analysis, layout dependency of defects. Critical area (CA) based yield analysis, Lithography based yield analysis. Metrology and physical failure analysis (PFA) techniques. Reliability related failure mechanisms such as hot carrier injection (HCI), negative temperature bias instability (NBTI), electromigration (EM) and electrostatic discharge (ESD). Mean time to failure (MTTF) analysis and design techniques to improve circuit and layout reliability and resiliency. (3 credits)

Prerequisites: Basic knowledge of VLSI design (e.g. ECE 558 or ECE 658)

Honesty Policy: Consultation with fellow students is encouraged, especially on projects. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. In addition, any collaborations or use of materials from previous courses, texts, solution manuals or advice from others should be clearly stated in the homework or lab report. Give credit where credit is due! Be honest about your own abilities and accomplishments!

Computer Requirements: The default CAD tools for all students are Cadence, Synopsys and Mentor electronic design automation tools. An example flow and a tutorial on the use of these tools are available at the TA Page. Since all the tools are Unix based, they can be accessed using any X-server program from machines running on MS Windows.

Project : Students are encouraged to work on projects that are forward looking with potential for external publication. Past research from this course has been published in respectable conferences such as SPIE and DATE. Project proposal process will be discussed in class.

UMass Calendar: http://www.umass.edu/registrar/gen_info/academic_calendar.htm

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