Verilog code examples from "Fundamentals of Digital Logic with Verilog Design" by S. Brown and Z. Vranesic, Mc.Graw-Hill, 2003.

Use these to familiarize yourself with Verilog and Quartus II.

[ Click here for the directory level view of the .v files listed below. ]

Simple combinational logic

2.32 (example1) - Structural, gate level specification of combinational logic
2.36 (example5) - Behavioral specification of combinational logic

Arithmetic functions

5.27 (adder4) - Foour bit adder composed of subcircuits
5.29 (addern) - Generic specification of a ripple-carry adder
5.34 (fulladd) - Behavioral specification of a full adder
6.39 (alu) - ALU 74381
6.45 (compare) - 4-bit comparator

MUXes, decoders/encoders

6.27 (mux2to1) - 2-to-1 MUX using conditioanal operator
6.35 (dec2to4) - 2-to-4 binary decoder
6.38 (seg7) - BCD-to-7-segment decoder
6.41 (priority) - 4-bit priority encoder

Flip-flops, registers, counters

7.35 (d_latch) - D latch
7.36 (flipflop) - D flipflop
7.39 (DFF_cascaded) - cascaded D flipflops
7.45 (flipflop_areset) - D flipflop with asynchronous reset
7.54 (shift4) - 4-bit shift register
7.55 (shiftn) - n-bit shift register
7.59 (updowncount) - Up/down n-bit counter
7.67 (trin) - n-bit tri-state buffer

Finate State Machines

8.29 (fsm_moore1a) - FSM type Moore with 2 always blocks, v. a
8.33 (fsm_moore1b) - FSM type Moore with 2 always blocks, v. b
8.34 (fsm_moore2) - FSM type Moore with a single always block
8.36 (fsm_mealy) - FSM typy Mealy with 2 always blocks