Instructor Office Hours and TA Lab Hours
Course Email Archive
Lab Report Format
Quartus II Resources
Quartus II Web Edition Software Version 7.1 SP1 by Altera
MIDI-OX MIDI Utility
AVR Studio 4 by Atmel
College of Engineering
Department of Electrical and Computer Engineering
Examples of Verilog code from Brown and Vranesic
A number of useful links regarding Verilog HDL
- Probably the best Verilog reference guide on the web:
- Verilog examples from Altera's website:
- Selected papers by C.E. Cummings on verilog coding
- File: v_simul-mismatch.pdf
- Title: RTL Coding Styles that Yield Simulation and Synthesis Mismatches
- Explains the reason for mismatches between pre-synthesis and post-synthesis
simulation and gives useful Verilog coding guidelines to avoid these problems.
- File: v_nonblock-assign.pdf
- Title: Nonblocking Assignments in Verilog Synthesis,
Coding Styles that Kill!
- Describes how Verilog blocking and nonblocking assignments are scheduled,
gives important coding guidelines to infer correct synthesizable logic.
- File: v_fsm-coding.pdf
- Title: Coding and Scripting for FSM Designs with Synthesis-Optimized,
- Describes design and synthesis techniques for finite state machine designs.
- *In computing, RAR is a proprietary file format for data compression and archiving.
The RAR file format was developed by Eugene Roshal (hence the name RAR: Roshal ARchive), who was born on March 10, 1972 in Russia and graduated from Chelyabinsk Technical University. He also developed programs for packing and unpacking RAR files, originally for DOS, and later ported to other platforms. [Source: http://en.wikipedia.org/wiki/Rar ]