Verilog Resources

Examples of Verilog code from Brown and Vranesic

• A number of useful links regarding Verilog HDL

  • Probably the best Verilog reference guide on the web:
    • On-line Verilog HDL Quick Reference Guide
      by Stuart Sutherland of Sutherland HDL, Inc.
  • Verilog examples from Altera's website:
    • General verilog examples
      
    • FSM (also available from the above listing)
      
      
• Selected papers by C.E. Cummings on verilog coding

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  • File: v_simul-mismatch.pdf
  • Title: RTL Coding Styles that Yield Simulation and Synthesis Mismatches
  • Explains the reason for mismatches between pre-synthesis and post-synthesis
    simulation and gives useful Verilog coding guidelines to avoid these problems.
    

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• File: v_nonblock-assign.pdf
• Title: Nonblocking Assignments in Verilog Synthesis,
  Coding Styles that Kill!
• Describes how Verilog blocking and nonblocking assignments are scheduled,
  gives important coding guidelines to infer correct synthesizable logic.

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• File: v_fsm-coding.pdf
• Title: Coding and Scripting for FSM Designs with Synthesis-Optimized,
  Glitch-Free Outputs
• Describes design and synthesis techniques for finite state machine designs.

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• *In computing, RAR is a proprietary file format for data compression and archiving.
  The RAR file format was developed by Eugene Roshal (hence the name RAR: Roshal ARchive), who was born on March 10, 1972 in Russia and graduated from Chelyabinsk Technical University. He also developed programs for packing and unpacking RAR files, originally for DOS, and later ported to other platforms. [Source: http://en.wikipedia.org/wiki/Rar ]