Power Considerations in Network Processor Design

Title: Power Considerations in Network Processor Design

Authors: Mark A. Franklin and Tilman Wolf

Abstract: Network processors are commonly implemented as systems-on-a-chip with multiple processors, caches, memory interfaces and I/O components on a single chip. Networking workloads lend themselves to exploiting high levels of parallelism with these chip-multiprocessors. The constraints of such a system lie in the maximum chip area and the maximum power consumption that are permissible for economic and technical reasons. We develop an analytic performance model that captures the processing performance and power consumption of such a system. Using a variety of metrics, we explore the design space of network processors and show the performance impact of different system and memory configurations.

Published: Mark A. Franklin and Tilman Wolf, "Power considerations in network processor design," in Proc. of Second Network Processor Workshop (NP-2) in conjunction with Ninth IEEE International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA, Feb. 2003, pp. 10-22.

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BibTeX:
@inproceedings{Franklin:PCN03,
   author    = {Franklin, Mark A. and Wolf, Tilman},
   title     = {Power Considerations in Network Processor Design},
   booktitle = {Proc. of Network Processor Workshop in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9)},
   year      = 2003,
   month     = feb,
   address   = {Anaheim, CA},
   pages     = {10--22}
}

Copyright: © 2003 Mark A. Franklin and Tilman Wolf.