Design Tradeoffs for Embedded Network Processors

Title: Design Tradeoffs for Embedded Network Processors

Authors: Tilman Wolf and Mark A. Franklin

Abstract: Demands for flexible processing have moved general-purpose processing into the data path of networks. With the development of System-On-a-Chip technology, it is possible to put a number of processors with memory and I/O components on a single ASIC. We present a performance model of such a system and show how the number of processors, cache sizes, and the tradeoffs between the use of on-chip SRAM and DRAM can be optimized in terms of computation per unit chip area for a given workload. Based on a telecommunications benchmark the results of such an optimization are presented and design tradeoffs for Systems-on-a-Chip are identified and discussed.

Published: Tilman Wolf and Mark A. Franklin, "Design tradeoffs for embedded network processors," in Proc. of International Conference on Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science), Karlsruhe, Germany, Apr. 2002, vol. 2299, pp. 149-164, Springer Verlag.

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BibTeX:
@inproceedings{Wolf:DTE02,
   author    = {Wolf, Tilman and Franklin, Mark A.},
   title     = {Design Tradeoffs for Embedded Network Processors},
   booktitle = {Proc. of International Conference on Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science)},
   year      = 2002,
   month     = apr,
   publisher = {Springer Verlag},
   address   = {Karlsruhe, Germany},
   pages     = {149--164},
   volume    = 2299
}

Copyright: © 2002 Springer Verlag. See Lecture Notes in Computer Science.