Project Overview

For cost and performance reasons, network processors are implemented as single-chip multiprocessors with on-chip memory and I/O interfaces. An important question is how to configure such a system-on-a-chip. More parallel processors provide more "processing cycles" at the cost of less on-chip memory. This leads to more cache misses, memory stalls, and finally lower processor utilization.

We have developed analytic performance models of network processors that consider a range of system and workload parameters to determine a variety of performance and cost metrics. Our initial model considers the following system parameters:

• Number and clock speed of processors.
• Number of hardware threads per processor
• Size of instruction and data caches.
• Bandwidth and number of memory channels
• Bandwidth of I/O channel.
• Off-chip memory speed

The performance criteria for such a system are:

• Processing power of the overall system
• Power consumption
• Chip area required for an implementation

The results of this work are twofold. For one, optimal configurations for a particular workload and technology parameters can be derived. The second, and probably more interesting, result is the quantitative performance impact when considering different configurations (e.g., how does power consumption change if the number of threads per processor is increased significantly?).

In a recent extension, we have extended the design space exploration to also consider the system topology. This allows the consideration of pipeline width and depth as well as the interconnect between system components and memory interfaces.

Publications

• Tilman Wolf and Mark A. Franklin, “Performance models for network processor design,” submitted to IEEE Transaction on Parallel and Distributed Systems.
• Ning Weng and Tilman Wolf, “Pipelining vs. multiprocessors - choosing the right network processor system topology,” in Proc. of Advanced Networking and Communications Hardware Workshop (ANCHOR 2004) in conjunction with The 31st Annual International Symposium on Computer Architecture (ISCA 2004), Munich, Germany, June 2004.
• Mark A. Franklin and Tilman Wolf, “Power considerations in network processor design,” in Proc. of Second Network Processor Workshop (NP-2) in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA, Feb. 2003, pp. 10–22.
• Tilman Wolf and Mark A. Franklin, “Design tradeoffs for embedded network processors,” in Proc. of International Conference on Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science), Karlsruhe, Germany, Apr. 2002, vol. 2299, pp. 149–164, Springer Verlag.
• Mark A. Franklin and Tilman Wolf, “A network processor performance and design model with benchmark parameterization,” in Proc. of First Network Processor Workshop (NP-1) in conjunction with Eighth International Symposium on High Performance Computer Architecture (HPCA-8), Cambridge, MA, Feb. 2002, pp. 63–74.
• Mark A. Franklin and Tilman Wolf, “Power considerations in network processor design,” in Network Processor Design: Issues and Practices, Volume 2, Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu, and Peter Z. Onufryk, Eds., chapter 3, pp. 29–50. Morgan Kaufmann Publishers, Nov. 2003.
• Mark A. Franklin and Tilman Wolf, “A network processor performance and design model with benchmark parameterization,” in Network Processor Design: Issues and Practices, Volume 1, Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, and Peter Z. Onufryk, Eds., chapter 6, pp. 117–138. Morgan Kaufmann Publishers, Oct. 2002.

For a complete list of NSL publications, see the publications page.