Computer networks have progressed from simple store-and-forward communication networks to systems where packets are not only forwarded, but also processed on routers. Network processors are becoming increasingly important components of such network systems. The performance demands on network processors require that these systems become more powerful to handle the increasing link speeds and application complexity. While CMOS technology provides increasing numbers of transistors per chip, it is not clear how next-generation network processors can make efficient use of this silicon real-estate. We explore the system architecture and configuration of next-generation network processors through analytic modeling that is closely tied in with workload analysis to explore this design space. The results of this work provide insights into new network processor architectures, give a quantitative understanding of design tradeoffs in network processor systems, and can be adapted to other system-on-a-chip applications.

Network processors also require highly optimized and fine-tuned software to achieve maximum performance. The embedded multiprocessor architecture of NPs makes it difficult for application developed to consider all possible system interactions when writing software. To alleviate this problem, we are developing a methodology to automatically profile and partition uniprocessor code for mapping and scheduling on NP systems.