Enclosed is a review of six VHDL books. The review is by Mircea Stan, mstan@risky.ecs.umass.edu Airiau, R.; Berge, J. M.; Olive, V. (CNET, France) Circuit synthesis with VHDL. Kluwer Academic Publishers, Norwell, MA, 1994, 240 pp., $89.95 ISBN 0-7923-9429-1. [Kluwer International series in engineering and computer science] Armstrong, James R.; and Gray, F. G. (Virginia Polytechnic Institute and State Univ., Blacksburg, VA) Structured logic design with VHDL. Prentice-Hall, Inc., Englewood Cliffs, NJ, 1993, 482 pp., ISBN 0-13-855206-1. Baker, Louis (Mission Research Corp., Abuquerque, NM) VHDL programming with advanced topics. John Wiley & Sons, Inc., New York, NY, 1993, 365 pp., ISBN 0-471-57464-3. Bhasker, Jayaram (AT&T Bell Labs., Murray Hill, NJ) A VHDL primer. (revised ed.) Prentice-Hall, Inc., Englewood Cliffs, NJ, 1995, 303 pp., ISBN 0-13-181447-8. [Prentice-Hall series in innovative technology.] Ott, Douglas E.; and Wilderotter, Thomas J. (ITT Avionics, Clifton, NJ) A designer's guide to VHDL Synthesis Kluwer Academic Publishers, Norwell, MA, 1994, 306 pp., $84, ISBN 0-7923-9472-0. Perry, Douglas L. (Redwood Design Automation) VHDL (2nd ed.) McGraw-Hill, Inc., New York, NY, 1994, 390 pp., $50, ISBN 0-07-049434-7. [McGraw-Hill series on computer engineering.] VHDL is the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language standardized as the ANSI/IEEE Std 1076 in 1987 (this version is known as VHDL'87) and reballoted in 1993 (VHDL'93). It is a strongly-typed, verbose language sometimes hard to understand with opponents calling it the Very ``Hard'' Description Language. The perception of VHDL as a non user-friendly language almost sparkled a ``religious war'' between VHDL and Verilog proponents and thus VHDL was fully embraced by users and CAD tool developers much later than expected (Verilog is another HDL initially developed by Cadence and now also in the public domain). VHDL was originally targeted at simulation and hardware documentation but most of its late success can be traced to applications in synthesis, testing and verification. VHDL is fully described in the Language Reference Manual (LRM) [1] but the LRM, although very accurate, is not enough for a designer to start using the language in a productive way. This is why there are many books about programming in VHDL for simulation or synthesis. The language is general, complex and you will probably need more than one book and a lot of hands-on experience in order to become really proficient. The six books reviewed here are some of the most recent ones and they cover most of the spectrum in terms of intended audience (from engineering student to professor, experienced designer and even manager), level of VHDL understanding (from beginner to experienced) and VHDL use (mainly documentation, simulation and synthesis). There is not much about formal verification using VHDL in any of these books. Almost all major publishers of VHDL books are represented, with the exception of Morgan Kaufmann [2]. Table 1: Descriptive Data ------------------------------------------------------------------------------------ | | Airiau | Armstrong | | | Ott | | | | Berge and | and | Baker | Bhasker | and | Perry | | | Olive | Gray | | |Wilderotter| | ------------------------------------------------------------------------------------ | no. of | 240 | 482 | 365 | 303 | 306 | 390 | | pages | | | | | | | ------------------------------------------------------------------------------------ | no. of | 7 | 9 | 16 | 12 | 11 | 12 | | chapters | | | | | | | ------------------------------------------------------------------------------------ | no. of | 1 | 1 | 1 | 4 | 1 | 4 | |appendices| | | | | | | ------------------------------------------------------------------------------------ | exercises| no | yes, | no | no | no | no | | | | 236 | | | | | ------------------------------------------------------------------------------------ |references| yes | yes, | yes, | yes | yes, but | no | | | | extensive | each chap.| | only a few| | ------------------------------------------------------------------------------------ | index | yes | yes | yes | yes | yes, | yes | | | | | | | short | | ------------------------------------------------------------------------------------ | purpose | tut./ref. | textbook | tut./adv. | tutorial | tutorial | tutorial | | | synthesis | | | | synthesis | reference | ------------------------------------------------------------------------------------ | edition | 1st. | 1st. | 1st. | 2nd. | 1st. | 2nd. | | | | | | | | | ------------------------------------------------------------------------------------ | year | 1994 | 1993 | 1993 | 1995 | 1994 | 1994 | | | | | | | | | ------------------------------------------------------------------------------------ | publisher| Kluwer | Prentice | Wiley | Prentice | Kluwer | McGraw | | | | Hall | | Hall | | Hill | ------------------------------------------------------------------------------------ Table 2: VHDL coverage ------------------------------------------------------------------------------------ | | Airiau | Armstrong | | | Ott | | | | Berge and | and | Baker | Bhasker | and | Perry | | | Olive | Gray | | |Wilderotter| | ------------------------------------------------------------------------------------ |which VHDL| VHDL'93 | VHDL'87 | VHDL'93 | VHDL'93 | VHDL'87 | VHDL'87 | | | | | | | | | ------------------------------------------------------------------------------------ | logic | STD_LOGIC | MVL4, MVL7| STD_LOGIC | MVL4 | STD_LOGIC | STD_LOGIC | | system | 1164 | Vantage | 1164, MVL5| | 1164 | 1164 | ------------------------------------------------------------------------------------ | VHDL | no | yes | yes | yes | no | yes | |simulation| | | | | | | ------------------------------------------------------------------------------------ | document.| yes | yes | yes | yes | yes | yes | | with VHDL| | | | | | | ------------------------------------------------------------------------------------ | VHDL | yes | yes | yes | no | yes | yes | | synthesis| | | | | | | ------------------------------------------------------------------------------------ | testing | yes | yes | yes | yes | yes | yes | | with VHDL| | | | | | | ------------------------------------------------------------------------------------ | formal | no | no | no | no | no | no | | verif. | | | | | | | ------------------------------------------------------------------------------------ | large | traffic | no | 1750A | no | no | vending | | example | light | | processor | | | machine | ------------------------------------------------------------------------------------ | target | synthesis | designers,| advanced | beginner | synthesis | beg./adv. | | audience | designers | academia | designers | designers | designers | designers | ------------------------------------------------------------------------------------ Airiau, Berge and Olive I found the Airiau, Berge and Olive book extremely well written and although it is not very long it covers in a thorough manner all aspects of VHDL synthesis. VHDL was initially developed for simulation and so not all language constructs are synthesizable. Focusing only on VHDL-based synthesis this book goes deeper than other books into the subject. Ch.1 ``About Synthesis'' defines the purpose of the book while Ch.2 ``VHDL Concepts'' is a short tutorial on VHDL. The authors use a clever methodology by presenting both a top-down synthesis flow in Ch.3 ``Mapping VHDL to Hardware'' and a bottom-up synthesis flow in Ch.4 ``Mapping Hardware to VHDL''. The idea in Ch.3 is to derive hardware implementations for common VHDL constructs while in Ch.4 several VHDL description styles are presented by starting with common hardware components (gates, muxes, latches, flip-flops, PLAs, etc.). All the examples given are useful as starting points for writing your own VHDL synthesizable code in either a top-down fashion (typically behavioral style at register transfer level (RTL)) or bottom-up one (typically structural style at RTL or gate level). Chapters 5 ``Design Methodology'' and 6 ``Synthesis Standard Environment'' show the big picture of how to integrate VHDL synthesis into existing design methodologies and synthesis environments. A comprehensive case study that describes and synthesizes the ubiquitous traffic light controller example concludes an excellent book on VHDL synthesis. Armstrong and Gray This is the only textbook among the six books and the only one written by professors. It has exercises at the end of each chapter (very good exercises) and it also has an excellent index and the best references. As the title suggests it is not a book about VHDL as a language, but about doing structured design with VHDL. The academic background of the authors can be seen from the start in the care with which they define the design process and the abstraction hierarchy in Ch.1 ``Structured Design Concepts'' and the CAD tool taxonomy in Ch.2 ``Design Tools''. Ch.3 gives some ``Basic Features of VHDL'' while Ch.4 goes into ``Basic VHDL Modeling Techniques''. The three design modeling levels as applied to VHDL are described in Ch.5 ``Algorithmic Level Design'', Ch.6 ``Register Level Design'' and Ch.7 ``Detailed Gate Level Design''. Ch.8 ``Multilevel Design'' describes more complex examples like Moore and Mealy state machines and microprogrammed control units. Ch.9 ``Algorithmic Synthesis'' deals with some high-level design topics that you won't find in any of the other books reviewed here like scheduling, allocation and automated synthesis of VHDL constructs. The Appendix describes the 4-valued logic system package used for many examples in the book. Although intended as a textbook for an undergraduate or graduate course in logic design the book can be a useful reference for practicing designers that want to understand digital design at a higher level of abstraction. In conjunction with some VHDL design software tools the book can be also used for a self-taught course with the help of the large number (236) of exercises. Solutions to the problems are not provided although I assume an instructor's manual with solutions is available from the publisher. Baker VHDL Programming with Advanced Topics by Louis Baker is probably the most ambitious of the six books in that it covers the broadest number of subjects including such exotic and non-related topics like Petri nets, semaphores, waveform relaxation and microprocessor superscalar architectures. Unfortunately there can be no depth when trying to address so many topics in a single book of this length and this can be also seen in the large number of chapters (16) which means that individual chapters are short (as short as 10 pages or less for chapters 4, 7, 8 and 9). Nonetheless the book can be useful for pointers to literature on the advanced topics discussed since it has good chapter-by-chapter references. Useful subjects mentioned here and not discussed in any of the other books are standardization efforts like: Waveform and Vector Exchange Specification (WAVES IEEE-Std 1029.1), Standard Delay Format (SDF), Electronic Data Interchange Format (EDIF ANSI/EIA-Std RS-548) and JTAG Boundary Scan Architecture (IEEE-Std 1149.1). The book is divided into two parts, the first part being a ``VHDL Tutorial'' and consisting of ten chapters: Ch.1 ``Introduction'', Ch.2 ``Signals'', Ch.3 ``Entity, Architecture, Configuration Statements'', Ch.4 ``Blocks and Guards'', Ch.5 ``Data'', Ch.6 ``Attributes'', Ch.7 ``Sequential Statements'', Ch.8 ``Concurrent Statements'', Ch.9 ``Packages, Libraries, Input/Output'' and Ch.10 ``VHDL-92 and Miscellaneous Topics''. The second part ``Using VHDL'' discusses more advanced topics in: Ch.11 ``VHDL Programming'', Ch.12 ``Discrete Event Simulation'', Ch.13 ``Finite State Machines'', Ch.14 ``Practical Considerations'', Ch.15 ``Microprocessors'' and Ch.16 ``Busses and Protocols''. The Appendix contains the two STANDARD and TEXTIO packages and information about changes from VHDL'87 to VHDL'93. I found the number of typographical errors in this book annoying. Bhasker The books by Baker and Bhasker are at two extremes: while ``VHDL Programming with Advanced Topics'' by L. Baker tries to leave nothing uncovered but in this way immediately becomes somehow superficial, ``A VHDL Primer'' by J. Bhasker represents a thorough coverage of VHDL basics. There are some VHDL advanced topics including VHDL synthesis that are not explored in this book but this leaves more room for explaining the important issues. The beginner will definitely appreciate this focus on introductory topics as well as the large number of examples. After a short Ch.1 ``Introduction'', Ch.2 presents ``A Tutorial'' that briefly introduces VHDL terminology, design units and modeling styles. These topics are later expanded in Ch.3 ``Basic Language Elements'', Ch.4 ``Behavioral Modeling'', Ch.5 ``Dataflow Modeling'', Ch.6 ``Structural Modeling'', Ch.7 ``Generics and Configurations'', Ch.8 ``Subprograms and Overloading'' and Ch.9 ``Packages and Libraries''. Some ``Advanced Features'' including aliases, type conversions, guarded signals, attributes and shared variables are presented in Ch.10. Ch.11 ``Model Simulation'' looks at the challenges of using VHDL for writing a test bench while Ch.12 ``Hardware Modeling Examples'' gives a thorough introduction of using VHDL for describing hardware. This chapter can be also used for synthesis in a bottom-up manner. The four Appendices are excellent. Appendix A ``Predefined Environment'' lists the VHDL'93 reserved words and the two standard VHDL packages: STANDARD and TEXTIO. Appendix B is a ``VHDL Syntax Reference'', Appendix C describes ATT_MVL, the 4-level logic system package used in the book while Appendix D gives a short but useful ``Summary of Changes'' from VHDL'87 to VHDL'93. The author has chosen to introduce topics in a gradual manner, with some basic information first, followed by a more advanced discussion in another chapter. This kind of treatment asks for a sequential reading and is valid when first learning the language. It becomes more of a problem though when trying to find a topic. Ott and Wilderotter A Designer's Guide to VHDL Synthesis is useful by providing a large number of examples that can be used and adapted for your own designs. If you have a clear picture of the VHDL synthesis process and need some more modeling examples this book is for you. Also if you are a manager trying to include VHDL synthesis in the design process there is some information for you here. The book is less structured than I would like though and this makes it rather hard to read and follow ideas. The first two chapters, ``Introduction'' and ``Making the Transition to VHDL Synthesis'' are so introductory that they are almost non-technical. Ch.3 ``VHDL Background for Synthesis'' defines VHDL constructs relevant to synthesis. Ch.4 ``Synthesis of Sequential Circuits'' has introductory examples of counter and state machine designs which are further refined in Ch.5 ``Sequential Counter Applications'' and in Ch.6 ``Control Logic and State Machines''. Adders, multipliers and register stacks are described in Ch.7 ``Data Processing Functions'' while general purpose combinational logic like gates, multiplexers, comparators and decoders are treated in Ch.8 ``Combinational Logic and Optimization''. The authors' choice of describing combinational circuits after sequential ones is somehow puzzling. Ch.9 ``Putting the Pieces Together'' discusses design hierarchies, complete ASIC designs and VHDL simulation and test bench generation. The last two chapters, Ch.10 ``Evaluating a Synthesis System'' and Ch.11 ``Future Prospects for ASIC Synthesis'' bring the discussion again to the non-technical level of the first two chapters, presumably in order to address the managerial audience. Perry For many designers the Perry book is their ``VHDL bible'' and with good reason. It is very well written in a top-down manner and in its 12 chapters you can find most of the information on VHDL you need. The beginner will find Ch.1 ``Introduction'' a very useful short VHDL tutorial followed by Ch.2 ``Behavioral Modeling'', Ch.3 ``Sequential Processing'' and Ch.4 ``Data Types''. The more advanced reader will appreciate Ch.5 ``Subprograms and Packages'', Ch.6 ``Predefined Attributes'', Ch.7 ``Configurations'' and Ch.8 ``Advanced Topics'', while the designer involved in VHDL synthesis will find essential reading in Ch.9 ``Synthesis'' and Ch.10 ``VHDL Synthesis'' as well as the comprehensive example of a vending machine in Ch.11 ``Top-Level System Design'' and Ch.12 ``Vending Machine: First Decomposition''. The four Appendices describe the STD_LOGIC_1164 9-value standard logic package used throughout the book, a rather unuseful, long and unreadable gate-level netlist of the vending machine example as compiled by the Synopsis Design Compiler, some interesting ``VHDL Reference Tables'' useful when writing VHDL descriptions and an explanation of the VHDL Bachus-Naur format (BNF) used in the LRM. The book is filled with many examples that can be used by the readers as starting points for their own designs. Being a 2nd edition also means that many of the bugs inherent in a 1st edition have been eliminated. Out of the six books the Perry book comes closest to a reference book. It will be especially useful for simulation but it can be also used for testing and synthesis. No book is perfect though and the Perry book has its minuses too. It is based on VHDL'87 and not on the newer VHDL'93 and this may soon mean a 3rd edition of this successful book will make the 2nd edition obsolete. There is not much information on VHDL structural modeling and the lack of a bibliography is annoying. Comparison All the six books reviewed here do a decent job at presenting basic VHDL terminology and VHDL design units like entity, architecture, configuration, package and package body. They also present a more or less clear perspective on VHDL modeling styles (behavioral, structural or mixed) and VHDL modeling levels (architectural, data flow, gate level or multilevel). Three of the books (the two synthesis ones and the Perry book) are based solely on the standardized 9-valued IEEE 1164 logic system. The Armstrong and Gray and the Baker books describe a series of different logic systems (4-valued, 7-valued, 46-valued, etc.) while the VHDL Primer by Bhasker uses only a simple 4-valued logic system. Depending on the publication date several of these books are based on the original VHDL'87 standard while others are based on the newer VHDL'93. It must be noted though that the changes from VHDL'87 to VHDL'93 are in general minor (there is an entire book explaining these changes [3]) and are done with upward compatibility in mind. Many commercial tools at the moment are not yet supporting VHDL'93. The VHDL standard was initially scheduled to be reballoted in 1992 and this is why in some of the books the new standard is called VHDL'92. There are other examples of conflicting terms or language misuse in these books as well: buses vs. busses, combinational vs. combinatorial logic, etc. The term behavioral modeling seems to be especially misused, for example in the Perry book it denotes modeling based on concurrent statements while in the Bhasker book it reflects sequentially executed procedural code. Recommendations As a general purpose reference book the Perry book remains my favorite. It can be successfully used by both beginners and advanced designers and a third edition should probably address the few remaining weak areas: lack of references, update to VHDL'93, more on structural modeling, better index. For someone, especially a beginner or someone who wants to use VHDL'93 now the Bhasker book can be a decent alternative. For someone involved in VHDL synthesis I recommend the Airiau, Berge and Olive book. It has a clear and most illuminating way of presenting arid topics. After reading it you really understand what VHDL synthesis is all about and you can start using it. If you need a lot of small coding examples the Ott and Wilderotter book will provide those. For the academically inclined reader, professor, student, researcher or even simple designer the Armstrong and Gray textbook is excellent. I really enjoyed reading it. It is also the only one providing exercises. As for the Baker book, if you know a lot about VHDL and you are looking for advanced topics you may find some references in here, but remember you'll also have to read those references since the book has a lot of breadth but not much depth. References [1] ANSI/IEEE Std 1076-1993 ``IEEE Standard VHDL Language Reference Manual'' Institute of Electrical and Electronics Engineers, Inc., N.Y., N.Y., June 1994. [2] P. Ashenden ``The designer's guide to VHDL'', Morgan Kaufmann Pub., San Mateo, CA, ISBN 1-55860-270-4. [3] J.M. Berge, A. Fonkoua, S. Maginot, J. Rouillard ``VHDL'92; the new features of VHDL'' Kluwer Academic Pub., ISBN 0-7923-9356-2.