664

ECE 664 VLSI Architectures

Description: This course explores the intersection and interplay of VLSI design and Computer Architecture. As such, both ECE 558/658 VLSI Design and ECE 568 or ECE 668 Computer Architectures are firm pre-requisites. The course briefly reviews the basics and history of VLSI design and Computer Architecture and then moves on to explore the trends, challenges and cutting edge research results spanning these areas. The course has no required textbook, but instead is based on both classical and recent papers from the literature. Students will learn how to critically read, summarize, and present research papers. Students will help to determine the reading list for the course based on their interests. Each student will make one oral presentation and one detailed review/critique of the papers. Extensions from the papers will be projects in the course. Projects will be individual unless special arrangements are made with the instructor. Final projects will be graded based on a final presentation and a final written report.

Instructor: Prof. Wayne Burleson, burleson (at) ecs.umass.edu, Knowles 309C,

Office hours Thurs/Fri 12-1.

Course Topics:

Review, History, Trends of Basic VLSI

Taxonomy of Architectures (Superscalar, VLIW, Multi-core)

Motivating Applications (General-purpose, Multimedia, DSP, Embedded, Network).

Metrics: Performance, Cost, Power, Reliability

Challenges: Power, Soft-errors, Interconnects, Memory Systems, Wear-out,

Course Objectives:

1. Learn about the current challenges which span VLSI and Architecture

2. Learn how previous generations have solved similar challenges

3. Learn how to critically read, summarize and extend a research paper

4. Extend one particular research approach and present significant results, possibly leading to publication.

Grading:

Paper presentation 25%

Paper review/critique/extend 25%

Final project 50% (10% proposal, 20% final presentation, 20% final report)

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Here are the proposed topics and presentation schedule
We will meet next week on Tuesday to confirm this schedule.
Then we will have a 2-week break with no meetings to
bootstrap the presentations.
Here is a draft schedule based on your preferences.
Each topic has a presenter and a reviewer. Each student
should appear once each as a Presenter and as a Reviewer.

Topic: Presenter Reviewer

Low-Power : Maithily Nagaraj
Memory Systems: Mike Maithily
FPGAs: Tariq Deepak
Sensor Network Architectures: Jeremy Ramakrishnan
RFID Archs.: Sravanthi Serge
Wear-out Aware: Adithya Mike
Interconnect Aware: Ramakrishnan Ibis
CAD Tools: Daniel Sravanthi
SOC: Deepak Jeremy
Security Archs; Serge Adithya
Soft-error Aware Archs: Ibis Tariq
Multi-core Nagaraj Daniel

Procedure:

1. Develop the reading list. Presenter and Reviewer together propose a list of at least 2 papers and get approval from Prof. Burleson at least 2 weeks before the presentation One paper should be an overview/survey/history paper, similar to the SER paper we looked at. Additional papers should be more recent and describe significant innovations. Review the course objectives for guidance. Be sure to include both architectural and VLSI issues. Provide full bibliographical citation, and links to the papers. Provide a short summary of the relevance of each paper. . All of this can happen via email.

2. The entire class will read all the papers. The presenter will prepare a 30 minute slide show of the papers. The reviewer will write a 10 page summary and review of the papers. Both presenter and reviewer should summarize the papers (50%), critique their assumptions, methods and results (25%) and suggest future directions (25%). Review the course objectives for guidance.

3. The entire class will evaluate the presentation using an evaluation form. I will evaluate your evaluations and summarize them all for the presenter.

Last modified 2/12/2008