FINAL TAPEOUT DESIGN REVIEW

The objective of this last design
review is to evaluate which chips should actually be sent out for
fabrication.  In addition, we will take a look back on the overall 
design process to see what worked, what didn't work, what we'd do 
differently next time, etc.   I will make final comments on your 
designs by early the following week to indicate which groups should 
proceed with tapeout.  

By the review you should be done with your chip and have completely 
verified the functional, physical, electrical and timing details of 
the final layout.  All of the workstations in the VLSI lab should be 
running some kind of verification at all times in the next 2 weeks.

At the design review you should present to me the following:

	1)  a full chip plot with padframe
	2)  selected plots of interesting sub-cells
	3)  a 2 page summary of your project including:
		-block diagram and use of the chip
		-list of novel features of your chip 
		-specifications: clock rate, number of transistors,
			power dissipation, technology
		-pin diagram and list
		-die size
		-design tools used
		-design time summary (person-hours for each task)
	4)  details of design process (who did what, what tools were
		good, what tools need improvement, what tools should
		be replaced, discussion of timing critical paths,
		discussion of bugs found during functional 
		verication, how many transistors drawn, etc.)  This 
		teaches me what to do for future versions of the 
		course and how you might do things differently in
		your future courses and jobs.

Be prepared to convince me that I should spend National Science
Foundation money to fabricate your chip.  I only have enough money
to fab about half of the chips in this course.  I will make my
decisions based on the likelihood that the chip will actually work.
This is a function of my overall opinion of the quality of the design
and the amount of verification that has been done.  I do not want us
to be in the embarassing position of having chips come back with vdd-vss
shorts.  Use the tools and your best analytical skills to make sure your
design will work.  Common problems in the past have involved connections
to the pad frame.  Make sure you understand the connectors on the pads
(input, output, enable).  Make sure power and clocks are properly routed
at the top level.

I am looking forward to seeing your finished chips.  As in past years,
I will be compiling a databook out of your data sheets and plots.  I
then distribute this databook to my colleagues at other universities
and industries.  Therefore I am interested in high quality work.
Make me proud!  


For the final writeup, I would like you to take a step 
back and do some analysis of the VLSI design process
using your own chip as a case study.  

	1.  For each major layout block as well as the 
entire chip, compute:
		a) n = the number of transistors, 
		b) d = number of drawn transistors, 
		c) n/d = the replication factor
		d) active area vs. routing area
		e) total area per block
		f) area vs. number of transistors 
		g) power consumption per block
		h) design time required for logic, circuit 
and layout of each block 

	2. Draw conclusions about the layout process.  Where 
did you spend your design time?  Where did you spend your 
area?  What additional CAD tools would have assisted the 
layout process?

	3. What is the critical timing path in your circuit?
What did you do to improve it?  What more could you do?

	4. Explain your clock generation and distribution 
strategy.  What is the total clock load (in pF)? What is
the worst case skew (in ns)?  What are the maximum and 
minimum clock rate (in Mhz)?

	5.  Suppose that we were suddenly able to scale your
design to .8u CMOS (lambda =.4).  How much faster, smaller
would your chip be?  Refer to Rabaey.

	6.  If I had extended the final deadline by
TWO weeks, what would you have done to improve:
		a) the probability of a correct design
		b) the layout of your chip
		c) the performance of your chip
		d) additional features
	   
	   Answer question 6 again, replacing TWO weeks 
by TEN weeks.  Note that the TWO weeks refers to incremental 
changes, while TEN weeks implies a complete re-design.

	7.  Discuss testing strategies for your chip.  What
did you do to improve testability?  (Note that 20% of a
recent Chip Design Contest won by UMASS students
was based on the testability of the chip)

	8.  What additional tools or improvements to the
existing tools would have been useful to better verify the 
correctness of your chip.  Schematic entry? Logic simulation?  
Circuit simulation?  Automatic routing from netlist? 

	9.  Include one color plot of your final design.  
Manually LABEL the major blocks.  (I will keep this copy)

	10.  Prepare a 2-page Web-page data sheet for your chip.
Include the following:
		a) name of chip, and designers
		b) rough block diagram
		c) short functional description
		d) pin list, package 
		e) technology
		f) no. of transistors
		g) clock rate
		h) estimated power consumption
		i) design style, tools used, design time
		j) special features(specific to each design)
		k) links to your files (sim, magic, cif, etc.) 
		l) links to relevant external sites

	Refer to an industrial chip data sheet for ideas on
format.  These data sheets will all be compiled into a booklet
so you must stick to the 2-page limit, although the 2 pages 
may be quite dense.  Please put some time into your data sheets
since I will be sending copies out to other schools and industry.
You may view datasheets from past years for ideas.


	-wayne