General Comments on Implementation Design Reviews 


Below are some details on what I expect. In general, this review
does not require much preparation beyond what 
you are doing to finish your chip.  The review will mainly 
consist of your TA and I reviewing your schematics, layouts, floorplans 
and simulations.   Be sure to be quantitative about area, delay,
power estimates. 
Do plan on who will present what and who will field 
questions about each portion of your chip.

At your presentation, you must show me:

	0) detailed block diagram of your system

	1) a tree diagram which indicates the design 
hierarchy  ( I should be able to refer to this to see
a cell's component cells and where it is instantiated)

	2) a full set of cell schematics and layouts (scale so 
that I can see transistors, well-ties, routing, etc.)

	3) higher-level schematic and layout plots  (for example, several
slices abutted to form a data path)

	4) a detailed floorplan showing clocking, power
routing, major busses and pad routing.

	5) selected simulation (both logic and circuit level)
results for proof of concept and to compare with earlier estimates.

	6) breakdown of time spent by each member on each task
and any problems encountered


I will grade your oral review based on your preparation and
your ability to answer my questions.  I will base the
grade for the written review on my evaluation of your project
web-site.

In preparation for Implementation Design Reviews, each group should
meet with the TA at least ONCE and preferably TWICE.  Layouts and
floorplans should be reviewed to avoid obvious problems.  

	Looking forward to seeing your work,

		-wayne