The feasibility review is a very important review and totals upto 35% of
your grade. Obviously, this demands more work than you must have done for
your proposal.

The project is designed to be like a real-life project you may work on in
the industry.  You have assigned yourself a project, divided the work and
looked at the different possible approaches you could use to finish your
project. The proposal review is where you proposed your ideas.

The next step now is to go deeper into your projects and specifically your
part individually, and show the feasibility of your ideas and
designs ("Feasibility Review"). A full functional definition of the tile
and its verification should be shown in the coming review. This is when
you should have set the specifications of your tile too. The design flow
must be precisely defined with an updated and realistic schedule.

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Oral presentation:

        Oral presentations will be 1/2 hour  Expect to sweat,
        dress informally.

        It is difficult to present your detailed designs in such
        a short time, consider it a challenge!

        Convince me and your TA that you know what is going
        on and that your design is feasible.

        Do NOT make slides of all of your schematics
        and simulations.  Just selected, interesting, ones.

        DO make slides of detailed block diagrams,
        floorplans, timing diagrams, cell hierarchies, etc.
        But be prepared to answer detailed questions by bringing
        all of your design materials.

        Recognize the fact that we know a lot about VLSI
        and a fair bit about your project.  Don't waste time
        stating the obvious.

        Try and predict what kinds of questions I will ask
        (based on the last review) and prepare convincing
        answers.

	Remember to finish your presentations in the time allotted, 
	else the group coming in second is affected.

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Check List:
	
	Full functional definition of the tile.

	Preliminary simulations and results.

	System Specifications (this will probably be your fist pass at it)

	Detailed floorplans.

	Clocking and power schemes.

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Web Report:

Be sure to explicitly include the following in your 
        web-site:  

	A well-organized home page and
	table of contents so that we can find things.

        Detailed block diagram of chip function

        SELECTED Logic and Timing simulations.
        (I do not need to see simulation of trivial 
        circuits, just the interesting/critical ones)

        Clocking scheme and timing design of blocks 
        (critical paths?, clock generation?, clock 
        distribution?, buffering of long and heavy loaded 
        lines?) This will make or break your chip!

        Detailed floorplan with area estimates of blocks routing and 
        I/O pin assignments (to avoid surprises when it comes to layout)

	Power estimates: (model, worst case, average case)

        External interfaces (ASOC, clock, power, configuration bus)

        Preliminary test plan  (design for test??)  This is related
        to external interfaces.  Make sure you can test both the
        functionality and the speed of your chip.  

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Best of Luck!!