ECE 558 Introduction to VLSI Design

ECE 658 (NTU IC740-A) VLSI Design Principles

Lecture 11 (Fall 2006)

EXAM 1 Review
The Exam is from 7-9pm on Tuesday, October 18 in ECSC0119.
Off-campus students should take the exam after they view lecture 11 and before Lecture 12.

· Topics

• Transistors

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• IV characteristic, sizing, Vthreshold, cross-section of MOSFET, body-effect, short-channel effects, scaling
• Inverter

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• VTC, V_M, Noise margins, Propagation time, Rise/fall time, regenerative property, power, ring oscillator
• Logic Styles (for each style: be able to draw schematic and layout and discuss sizing, noise margins, timing, power, size)

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• Static CMOS
• Pseudo-NMOS
• Pass transistor logic (just know CPL)
• Timing of multiple gate circuit (for example NAND2 driving INV driving NOR2).  How fast?  Fan-in, fan-out, sizing rules, capacitance.
• Layout (be able to read a layout and provide schematic, sizes and parasitic capacitances.
• Note for 658 students: In addition to all the questions for the 558 students, I will ask a few questions about more advanced topics. Examples include impact of short-channel effects, timing of CPL, multi-level logic, 
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• Examples

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• Refer to HW1 and HW2
• Strategy

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• Plan your time at the beginning of the exam according to point values on each question
• Read through entire exam before starting
• Ask a question before spending too much time on something you are not sure of
• In most cases, you will get almost total credit if you just have an expression rather than a number for a particular answer.  Don't waste time with your calculator (you may not even need one)

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• Rules
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   Single 8.5 x 11in sheet of notes allowed (both sides).  Don't worry about copying the physical constants from the book